Abstract: An information processor, a method for controlling cache flush, and an information processing controller that increases the data processing speed by efficiently performing cache flushing on a cache memory. A CPU includes a load/store unit and a flush control unit. The CPU controls data stored in a cache through a cache controller. When detecting an “.f” signal, the flush control unit waits until a single cache line is accessed. When determining that a single cache line has been accessed, the flush control unit issues a cache flush instruction to a cache controller.