Patents by Inventor Nagaraj Ashok Putti

Nagaraj Ashok Putti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240012771
    Abstract: The described techniques and apparatuses enable memory-request priority up-leveling. A memory request is received over a virtual channel, VC, and is then added to a memory-request buffer with an original priority-level for the memory request and an indication that the memory request is associated with a virtual channel identification, VCID, of the VC. Related memory requests within the memory-request buffer are also indicated as being associated with the VCID. Responsive to determining that an up-level indication for the VCID is asserted over a side channel, the original priority-levels of the memory request, and other memory-requests in the memory-request buffer having an indication of the VCID, are increased to respective up-leveled priority levels. Responsive to determining that the up-level indication is no longer asserted, the up-leveled priority levels are returned to respective original priority-levels.
    Type: Application
    Filed: November 5, 2020
    Publication date: January 11, 2024
    Applicant: Google LLC
    Inventors: Nagaraj Ashok Putti, Gopi Neela, Shubham Mahajan, Praxal Sunilkumar Shah
  • Publication number: 20240004551
    Abstract: This document describes systems and techniques for modulating credit allocations in memory subsystems. The described systems and techniques can provide a feedback mechanism to a credit controller to improve the bandwidth at a memory interface. The memory controller monitors statistics associated with transaction requests served to one or more random access memories (RAMs) of the memory subsystem. The memory controller can then provide suggestions to the credit controller or to the one or more clients to modulate the number of credits allocated to one or more clients. In this way, the described systems and techniques can improve the efficiency of the memory controller in managing the transaction requests and the bandwidth at the memory interface.
    Type: Application
    Filed: October 26, 2020
    Publication date: January 4, 2024
    Applicant: Google LLC
    Inventors: Nagaraj Ashok Putti, Abhra Bagchi, Vyagrheswarudu Durga Nainala, Venkateswaran Ananthanarayanan
  • Publication number: 20230342314
    Abstract: Techniques and apparatuses are described that enable memory request timeouts using a common counter. A memory request is received, and a common count timeout is generated for the memory request based on a common count at a time of receipt and a latency requirement of the memory request. Common count timeouts of one or more related memory requests within a memory request buffer (if they exist) are adjusted as needed, and the memory request is placed in the memory request buffer. The common count is incremented, and the memory request is indicated as timed out in response to an incrementation of the common count matching the common count timeout for the memory request.
    Type: Application
    Filed: September 14, 2020
    Publication date: October 26, 2023
    Applicant: Google LLC
    Inventors: Nagaraj Ashok Putti, Vyagrheswarudu Durga Nainala, Gopi Neela, Abhra Bagchi