Abstract: The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.

Abstract: Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.

Abstract: Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.

Abstract: Techniques for intelligent tuning of speed models for configurable integrated circuits. The techniques consider data related to yield, quality-of-results, and data for individual programmable-interconnect-point (PIP)-contexts. More specifically, the speed of yield-related structures, quality-of-results related structures, and structures for measuring individual PIP-contexts are measured. These measurements are compared with estimated values stored as part of a speed model and scaling factors for the stored estimated values are calculated. The scaling factors are applied to the estimated values within the speed model and measurements are repeated if desired.

Abstract: An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.

Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.

Abstract: Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.

Abstract: Techniques for using a speed measurement circuit to measure speed of an integrated circuit. The speed measurement circuit includes a ring oscillator and a counter circuit. The ring oscillator includes an AND gate with an inverting input and a non-inverting input. The ring oscillator also includes a programmable interconnect point context (PIP-context) having a first programmable interconnect point (PIP), a first interconnect, a second PIP, and a second interconnect coupled in series. The ring oscillator also includes a third interconnect and a third PIP coupled in series with the PIP-context and with an inverting input of the AND gate. The counter circuit is coupled to an output of the AND gate and configured in the programmable integrated circuit.

Abstract: Approaches for generating delay values for instances of a circuit include inputting possible contexts of the circuit. Each context includes a respective delay value and a combination of possible types of a plurality of characteristics of the circuit, and each characteristic is of one type of a plurality of alternative types of the characteristic. A plurality of classification parameters is input and the classification parameters indicate selected ones of the characteristics. Groups of contexts are selected based on the plurality of classification parameters. Each group includes one or more of the contexts, and each context includes the plurality of characteristics. A combination of types of the selected characteristics in each context in a group is equal to the combination of types of the selected characteristics of each other context in the group. For each group, a mean and a standard deviation of the respective delay values are determined and output.

Abstract: Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.

Abstract: Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.

Abstract: The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern.

Abstract: With the evolution of technology, there is a continual demand for enhanced speed, capacity and efficiency. A modular, chip testing system associated with a single chip on a wafer is described. This system includes a performance structure for measuring chip performance during a testing period; a power structure for measuring chip power during the testing period; an interconnect structure for measuring characteristics of interconnects within the chip during the testing period; a device structure for measuring characteristics of devices within the chip during the testing period; and a plurality of probe pads coupled to the performance structure, power structure, interconnect structure, and the device structure, wherein the plurality of probe pads receive signals during the testing period that enable the modular, chip testing system to measure characteristics of the interconnects, characteristics of the devices, chip power, and chip performance.

Abstract: The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern.

Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference oscillators overlying a substrate of the wafer; measuring the frequencies of the reference oscillators as influenced by transistor characteristics, intra structure parasitics, resistive, capacitive and inductive parasitics; and isolating the inductive parasitics by the appropriate comparisons between the reference oscillators.

Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a plurality of selectable devices under test (DUT) overlying a substrate of the wafer; biasing a second structure located in proximity to the DUT to have a first electrical state such that a first equivalent test structure is formed; determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter; biasing the second structure to have a second electrical state such that a second equivalent test structure is formed; and determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.

Abstract: The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each mode from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.