Patents by Inventor NAGARAJAN SETHURAMAN

NAGARAJAN SETHURAMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110125302
    Abstract: A method and system is provided for verifying and certifying the safety logic of a manufacturing automation system including safety logic, where the logic may include one or more safety modules, routines, programs and tasks or a combination thereof; testing specifications corresponding to the safety logic; one or more formal model generators adapted for automatically transforming the safety logic and testing specifications through a logic parser into their respective mathematical models, formatted for example, as a Petri-net or binary decision diagram; a safety logic verifier configured for automatically comparing the safety logic formal model against the testing specification formal model to verify the safety logic model for the purpose of certifying the safety logic. The testing specifications may include testing of safety logic behavior including reaching safe state, remaining in safe state without reset, recovering from safe state with reset and remaining active with false alarm detection.
    Type: Application
    Filed: October 23, 2009
    Publication date: May 26, 2011
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: Nagarajan Sethuraman, Jerome O. Schroeder, Soumen De, Chengyin Yuan, Stephan R. Biller, Frank Gajor, Jeffrey J. Byrnes, Narahari K. Hunsur
  • Publication number: 20090182442
    Abstract: A system and method for interpreting formal verification results of PLC logic code used to control a manufacturing process, or other automated process, where the interpretation process does not require highly skilled technicians having significant experience in computer and mathematical algorithms. The verification process includes providing a verification results summary to check the compliance of the code with respect to the specifications. The verification results summary is analyzed and categorized to determine whether violations or errors are found in the results. The results can be depicted by assertion trees if a direct assertion between the PLC logic and the specifications can be provided. Alternatively, the results can be depicted by a reduced ladder logic if a direct assertion between the PLC logic and the specifications cannot be provided and a simulation is required. The specification refinement suggestions will be provided if the critical variable for violations is identified.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 16, 2009
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: NAGARAJAN SETHURAMAN, Soumen De, Chengyin Yuan, Narahari K. Hunsur