Patents by Inventor Nagarajan Subramaniyan

Nagarajan Subramaniyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200159679
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Ramdas P. KACHARE, Fred WORLEY, Harry ROGERS, Wentao WU, Nagarajan SUBRAMANIYAN
  • Patent number: 10585843
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Patent number: 10585819
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Publication number: 20190272241
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction.
    Type: Application
    Filed: September 6, 2018
    Publication date: September 5, 2019
    Inventors: Ramdas P. KACHARE, Fred WORLEY, Harry ROGERS, Wentao WU, Nagarajan SUBRAMANIYAN
  • Publication number: 20190272240
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 5, 2019
    Inventors: Ramdas P. KACHARE, Fred WORLEY, Harry ROGERS, Wentao WU, Nagarajan SUBRAMANIYAN
  • Patent number: 10073805
    Abstract: Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 11, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Rajendran Vishwanathan, Nagarajan Subramaniyan, Jeffrey Michael Dodson, Jack Regula
  • Publication number: 20170068636
    Abstract: Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 9, 2017
    Inventors: Rajendran Vishwanathan, Nagarajan Subramaniyan, Jeffrey Michael Dodson, Jack Regula
  • Patent number: 9223734
    Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 29, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nagarajan Subramaniyan, Jeffrey Michael Dodson, Jack Regula
  • Publication number: 20150281126
    Abstract: A method of transferring data over a switch fabric with at least one switch with an embedded network class endpoint device is provided. At a device transmit driver a transfer command is received to transfer a message. If the message length is less than a threshold the message is pushed. If the message length is greater than the threshold, the message is pulled.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 1, 2015
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Jeffrey M. DODSON, Nagarajan SUBRAMANIYAN
  • Patent number: 9141571
    Abstract: A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: September 22, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
  • Publication number: 20150254082
    Abstract: A method of remote booting over PCI Express using a synthetic remote boot capability is provided. A management host software system intercepts probe requests from a host and provided information required for a remote boot. The management host software system may include expansion ROM information to support different host architectures. A synthetic device booting capability may be shown to a host, including the expansion ROM information. Additional support for DHCP and TFTP may be provided.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 10, 2015
    Applicant: PLX Technology, Inc.
    Inventors: Rajendran VISHWANATHAN, Nagarajan SUBRAMANIYAN, Jeffrey M. DODSON, Jack REGULA
  • Publication number: 20150169487
    Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Inventors: Nagarajan SUBRAMANIYAN, Jeffrey Michael DODSON, Jack REGULA
  • Publication number: 20150127878
    Abstract: Tunneled window connections are utilized in a switch fabric to perform programmed input output transfers. The window connections are based on global IDs. A management entity may enforce the tunneled window connections, improving security.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Nagarajan SUBRAMANIYAN, Jeffrey M. DODSON
  • Publication number: 20150019789
    Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.
    Type: Application
    Filed: October 1, 2014
    Publication date: January 15, 2015
    Inventors: Nagarajan SUBRAMANIYAN, Jack REGULA, Jeffrey M. DODSON
  • Patent number: 8880771
    Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: November 4, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
  • Publication number: 20140237156
    Abstract: PCIe is a point-to-point protocol. A PCIe switch fabric has multi-path routing supported by adding an ID routing prefix to a packet entering the switch fabric. The routing is converted within the switch fabric from address routing to ID routing, where the ID is within a Global Space of the switch fabric. Rules are provided to select optimum routes for packets within the switch fabric, including rules for ordered traffic, unordered traffic, and for utilizing congestion feedback. In one implementation a destination lookup table is used to define the ID routing prefix for an incoming packet. The ID routing prefix may be removed at a destination host port of the switch fabric.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 21, 2014
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Jeffrey M. DODSON, Nagarajan SUBRAMANIYAN
  • Publication number: 20140122765
    Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Nagarajan SUBRAMANIYAN, Jack REGULA, Jeffrey Michael DODSON
  • Patent number: 8645605
    Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: February 4, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
  • Publication number: 20120167085
    Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.
    Type: Application
    Filed: August 18, 2011
    Publication date: June 28, 2012
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Nagarajan SUBRAMANIYAN, Jack REGULA, Jeffrey Michael DODSON
  • Publication number: 20050086349
    Abstract: A method for optimizing a network connection between a first device and a second device, the first device comprising a first packet protocol and a second packet protocol, the first packet protocol comprising a connection setup portion, the second protocol comprising a data transfer portion. The method includes initiating the network connection from the first device to said second device using the first packet protocol. The method further includes receiving an acknowledgement from the second device; and, initiating a data transfer between the first device and the second using the second packet protocol.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 21, 2005
    Inventor: Nagarajan Subramaniyan