Abstract: The invention relates to system with a processing unit housed on a chip that includes a microprocessor to read and/or write in an external memory via a bus. The system includes an address protection unit that includes a swap unit implementing an address permutation scheme to protect information leakage from the bus, a permutation table maintaining a mapping between real address called by the microprocessor and masked address used by the swap unit to address the external memory, a shuffle buffer containing M slots among N slots of the memory address space, and a counter table containing one counter per slot of said N slots, wherein memory addresses are considered in bunches. The system also includes a flag unit containing a flag per bunch, and an update unit that triggers an update algorithm when the flag has changed to a predetermined value.