Patents by Inventor Nagarjuna Duvvuru

Nagarjuna Duvvuru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200380745
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. The apparatus can determine visibility information for each of a plurality of primitives in a first viewpoint or any available viewpoint of an image. In some aspects, the visibility information can include information regarding whether the primitive is visible in the first viewpoint. The apparatus can also determine a visibility stream based on the determined visibility information for each of the plurality of primitives in the first viewpoint. Additionally, the apparatus can identify at least one of the plurality of primitives in the first viewpoint as not visible based on the determined visibility information. The apparatus can also determine to skip rendering the plurality of primitives in the first viewpoint identified as not visible. Further, the apparatus can send and store the visibility stream in the buffer and retrieve the visibility stream from the buffer.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: Kalyan Kumar BHIRAVABHATLA, Viswanath Shashikant NIKAM, Suvam CHATTERJEE, Nagarjuna DUVVURU
  • Patent number: 9959665
    Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Nagarjuna Duvvuru, Tao Wang, Jian Liang, Chunlin Wang
  • Publication number: 20170024926
    Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.
    Type: Application
    Filed: July 21, 2015
    Publication date: January 26, 2017
    Inventors: Nagarjuna Duvvuru, Tao Wang, Jian Liang, Chunlin Wang
  • Patent number: 9436263
    Abstract: A voltage and frequency scaling system for a processor is provided that may be implemented in dedicated logic or in software. The various voltage and frequency settings for the processor comprise a set of performance settings. The system includes a profiler module that maps each performance setting to a workload range for the processor. The profiler module also maps each workload range to a profiled throughput for the processor. Using a predicated average throughput from the mapping, the voltage and frequency scaling system advantageously selects from the performance settings and commands the processor to operate according to the selected performance setting.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: September 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Vinay Reddy Venumuddala, Nagarjuna Duvvuru, Gur Prasad Srivastava
  • Publication number: 20150241942
    Abstract: A voltage and frequency scaling system for a processor is provided that may be implemented in dedicated logic or in software. The various voltage and frequency settings for the processor comprise a set of performance settings. The system includes a profiler module that maps each performance setting to a workload range for the processor. The profiler module also maps each workload range to a profiled throughput for the processor. Using a predicated average throughput from the mapping, the voltage and frequency scaling system advantageously selects from the performance settings and commands the processor to operate according to the selected performance setting.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Vinay Reddy Venumuddala, Nagarjuna Duvvuru, Gur Prasad Srivastava