Abstract: A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method for inter-processor core message passing by allocating dedicated address space of the on-chip memory for each processor with exclusive write access. Each of the multiple processor cores maintains a dedicated cache while maintaining coherency with the non-cache shared memory.