Patents by Inventor Nagatoshi Ooki

Nagatoshi Ooki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11022372
    Abstract: An air conditioner that includes a heat exchanger including: heat-transfer pipes extending in a horizontal direction and spaced apart at predetermined intervals in a vertical direction and configured to allow a thermal medium to flow therein. A part of the heat transfer pipes are used for at least one inflow path into which the thermal medium flows from the outside of the heat exchanger and the other part of the heat transfer pipes are used for at least one outflow path from which the thermal medium flows out to the outside. At least one connection pipe through which an outlet side of one of the at least one inflow path communicates with an inlet side of one of the at least one outflow path.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 1, 2021
    Assignee: HITACHI-JOHNSON CONTROLS AIR CONDITIONING, INC.
    Inventors: Shuuhei Tada, Kenji Matsumura, Nagatoshi Ooki, Mamoru Houfuku, Takeshi Endo
  • Publication number: 20200185523
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
  • Publication number: 20190120556
    Abstract: An outdoor device is provided which has: a heat exchanger including a heat exchange portion having multiple heat transfer pipes and multiple heat transfer fins joined to the heat transfer pipes, and a pair of header pipe assemblies arranged substantially in parallel along the upper-to-lower direction to face each other and configured to bundle end portions of the heat transfer pipes extending from the heat exchange portion; and a housing configured to support the heat exchanger via a support bracket. The support bracket includes a heat exchange side holding portion, a housing side holding portion, and a fin contact portion provided integrally with the heat exchange side holding portion or the housing side holding portion and arranged in contact with or in proximity to an edge portion of the heat exchange portion adjacent to one of the header pipe assemblies.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Nagatoshi OOKI, Shuuhei TADA, Mamoru HOUFUKU, Takeshi ENDO
  • Publication number: 20180306515
    Abstract: An air conditioner that includes a heat exchanger including: heat-transfer pipes extending in a horizontal direction and spaced apart at predetermined intervals in a vertical direction and configured to allow a thermal medium to flow therein. A part of the heat transfer pipes are used for at least one inflow path into which the thermal medium flows from the outside of the heat exchanger and the other part of the heat transfer pipes are used for at least one outflow path from which the thermal medium flows out to the outside. At least one connection pipe through which an outlet side of one of the at least one inflow path communicates with an inlet side of one of the at least one outflow path.
    Type: Application
    Filed: June 27, 2018
    Publication date: October 25, 2018
    Inventors: Shuuhei TADA, Kenji MATSUMURA, Nagatoshi OOKI, Mamoru HOUFUKU, Takeshi ENDO
  • Publication number: 20180269323
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
  • Patent number: 9978869
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20160351713
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: August 9, 2016
    Publication date: December 1, 2016
    Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
  • Patent number: 9412669
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: August 9, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20150132904
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
  • Patent number: 8963250
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Patent number: 7705402
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: April 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20090039427
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: October 15, 2008
    Publication date: February 12, 2009
    Inventors: Akihiro SHIMIZU, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20080303091
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 11, 2008
    Inventors: Akihiro SHIMIZU, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Patent number: 7414293
    Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: August 19, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Patent number: 7411253
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20070102768
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: December 20, 2006
    Publication date: May 10, 2007
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20070023843
    Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.
    Type: Application
    Filed: October 3, 2006
    Publication date: February 1, 2007
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Monaka, Katsuhiko Ichinose
  • Patent number: 7115954
    Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: October 3, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Patent number: 7105394
    Abstract: A method of manufacturing a semiconductor device having an n-type FET and p-type FET, each formed over a semiconductor substrate, calls for (a) forming, over the n-type FET and p-type FET, a first insulating film, for generating a tensile stress in the channel formation region of the n-type FET, to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film, for generating a compressive stress in the channel formation region of the p-type FET, to cover gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 12, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., LTD
    Inventors: Kiyota Hachimine, Akihiro Shimizu, Nagatoshi Ooki, Satoshi Sakai, Naoki Yamamoto
  • Publication number: 20040029323
    Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.
    Type: Application
    Filed: August 13, 2003
    Publication date: February 12, 2004
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose