Patents by Inventor Nagatoshi Ooki
Nagatoshi Ooki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11022372Abstract: An air conditioner that includes a heat exchanger including: heat-transfer pipes extending in a horizontal direction and spaced apart at predetermined intervals in a vertical direction and configured to allow a thermal medium to flow therein. A part of the heat transfer pipes are used for at least one inflow path into which the thermal medium flows from the outside of the heat exchanger and the other part of the heat transfer pipes are used for at least one outflow path from which the thermal medium flows out to the outside. At least one connection pipe through which an outlet side of one of the at least one inflow path communicates with an inlet side of one of the at least one outflow path.Type: GrantFiled: June 27, 2018Date of Patent: June 1, 2021Assignee: HITACHI-JOHNSON CONTROLS AIR CONDITIONING, INC.Inventors: Shuuhei Tada, Kenji Matsumura, Nagatoshi Ooki, Mamoru Houfuku, Takeshi Endo
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Publication number: 20200185523Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Publication number: 20190120556Abstract: An outdoor device is provided which has: a heat exchanger including a heat exchange portion having multiple heat transfer pipes and multiple heat transfer fins joined to the heat transfer pipes, and a pair of header pipe assemblies arranged substantially in parallel along the upper-to-lower direction to face each other and configured to bundle end portions of the heat transfer pipes extending from the heat exchange portion; and a housing configured to support the heat exchanger via a support bracket. The support bracket includes a heat exchange side holding portion, a housing side holding portion, and a fin contact portion provided integrally with the heat exchange side holding portion or the housing side holding portion and arranged in contact with or in proximity to an edge portion of the heat exchange portion adjacent to one of the header pipe assemblies.Type: ApplicationFiled: December 18, 2018Publication date: April 25, 2019Inventors: Nagatoshi OOKI, Shuuhei TADA, Mamoru HOUFUKU, Takeshi ENDO
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Publication number: 20180306515Abstract: An air conditioner that includes a heat exchanger including: heat-transfer pipes extending in a horizontal direction and spaced apart at predetermined intervals in a vertical direction and configured to allow a thermal medium to flow therein. A part of the heat transfer pipes are used for at least one inflow path into which the thermal medium flows from the outside of the heat exchanger and the other part of the heat transfer pipes are used for at least one outflow path from which the thermal medium flows out to the outside. At least one connection pipe through which an outlet side of one of the at least one inflow path communicates with an inlet side of one of the at least one outflow path.Type: ApplicationFiled: June 27, 2018Publication date: October 25, 2018Inventors: Shuuhei TADA, Kenji MATSUMURA, Nagatoshi OOKI, Mamoru HOUFUKU, Takeshi ENDO
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Publication number: 20180269323Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: May 21, 2018Publication date: September 20, 2018Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Patent number: 9978869Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: August 9, 2016Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20160351713Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: August 9, 2016Publication date: December 1, 2016Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Patent number: 9412669Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: January 22, 2015Date of Patent: August 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20150132904Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: January 22, 2015Publication date: May 14, 2015Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Patent number: 8963250Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: October 15, 2008Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Patent number: 7705402Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: August 12, 2008Date of Patent: April 27, 2010Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20090039427Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: October 15, 2008Publication date: February 12, 2009Inventors: Akihiro SHIMIZU, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20080303091Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: August 12, 2008Publication date: December 11, 2008Inventors: Akihiro SHIMIZU, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Patent number: 7414293Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.Type: GrantFiled: October 3, 2006Date of Patent: August 19, 2008Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Patent number: 7411253Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: December 20, 2006Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20070102768Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: December 20, 2006Publication date: May 10, 2007Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20070023843Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.Type: ApplicationFiled: October 3, 2006Publication date: February 1, 2007Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Monaka, Katsuhiko Ichinose
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Patent number: 7115954Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.Type: GrantFiled: June 29, 2001Date of Patent: October 3, 2006Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Patent number: 7105394Abstract: A method of manufacturing a semiconductor device having an n-type FET and p-type FET, each formed over a semiconductor substrate, calls for (a) forming, over the n-type FET and p-type FET, a first insulating film, for generating a tensile stress in the channel formation region of the n-type FET, to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film, for generating a compressive stress in the channel formation region of the p-type FET, to cover gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.Type: GrantFiled: December 31, 2002Date of Patent: September 12, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., LTDInventors: Kiyota Hachimine, Akihiro Shimizu, Nagatoshi Ooki, Satoshi Sakai, Naoki Yamamoto
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Publication number: 20040029323Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.Type: ApplicationFiled: August 13, 2003Publication date: February 12, 2004Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose