Patents by Inventor Nagatoshi Tsunoda

Nagatoshi Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063071
    Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Jeffery Bielefeld, Adel Elsherbini, Bhaskar Jyoti Krishnatreya, Feras Eid, Gauri Auluck, Kimin Jun, Mohammad Enamul Kabir, Nagatoshi Tsunoda, Renata Camillo-Castillo, Tristan A. Tronic, Xavier Brun
  • Publication number: 20240063142
    Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Botao Zhang, Yi Shi, Haris Khan Niazi, Feras Eid, Nagatoshi Tsunoda, Xavier Brun, Mohammad Enamul Kabir, Omkar Karhade, Shawna Liff, Jiraporn Seangatith
  • Publication number: 20220102305
    Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Bhaskar Jyoti Krishnatreya, Nagatoshi Tsunoda, Shawna M. Liff, Sairam Agraharam
  • Publication number: 20220020716
    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
  • Patent number: 11183477
    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
  • Publication number: 20210098411
    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
  • Patent number: 4630519
    Abstract: An electromechanical vibrator driving device comprising a rhythm signal generator to produce rhythmic pulses in a pattern corresponding to a beat pattern of a selected music rhythm, the rhythmic pulses being amplified and then applied to the vibrator so that the vibrator generates a rhythmical vibration of the selected music rhythm. The rhythm signal generator comprises a rhythm pattern generator storing different rhythm patterns and providing pulses corresponding to strong beats and pulses corresponding to weak beats in a selected rhythm pattern, separately. The strong beat pulses and the weak beat pulses are processed by attenuators to have different amplitudes and are mixed to produce the rhythm signal.
    Type: Grant
    Filed: June 21, 1985
    Date of Patent: December 23, 1986
    Inventors: Mutsuo Hirano, Nagatoshi Tsunoda
  • Patent number: RE32980
    Abstract: An electromechanical vibrator driving device comprising a rhythm signal generator to produce rhythmic pulses in a pattern corresponding to a beat pattern of a selected music rhythm, the rhythmic pulses being amplified and then applied to the vibrator so that the vibrator generates a rhythmical vibration of the selected music rhythm. The rhythm signal generator comprises a rhythm pattern generator storing different rhythm patterns and providing pulses corresponding to strong beats and pulses corresponding to weak beats in a selected rhythm pattern, separately. The strong beat pulses and the weak beat pulses are processed by attenuators to have different amplitudes and are mixed to produce the rhythm signal.
    Type: Grant
    Filed: December 3, 1987
    Date of Patent: July 11, 1989
    Assignee: Sanden Corporation
    Inventors: Mutsuo Hirano, Nagatoshi Tsunoda