Patents by Inventor Nagendra Chandrakar

Nagendra Chandrakar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast cyclic decoder circuit for FIFO/LIFO data buffer
    Patent number: 8238187
    Abstract: Embodiments of systems and methods for improved first-in-first-out (FIFO), last-in-last out (LIFO) and full-cycle decoders are described herein. In the various embodiments of the system, a clock generator is operable to generate a clock signal having an active phase and an inactive phase. A set of monotonic flip-flops are operable to capture a set of incoming data addresses during the active cycle of the clock and to generate therefrom data corresponding to single bits in the addresses that have changed compared to the data addresses received by the set of monotonic flip-flops during an immediately preceding data capture cycle. A set of static flip-flops are operable to capture a set of incoming data addresses during the inactive phase of the clock cycle and to generate set output data therefrom. A decoder operable to process the set output data from the set of static flip-flops and to generate a set of old wordlines corresponding to a set of data addresses in the immediately preceding data capture cycle.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Animesh Jain, Nagendra Chandrakar, Sonia Ghosh
  • Fast Cyclic Decoder Circuit for FIFO/LIFO Data Buffer
    Publication number: 20120026819
    Abstract: Embodiments of systems and methods for improved first-in-first-out (FIFO), last-in-last out (LIFO) and full-cycle decoders are described herein. In the various embodiments of the system, a clock generator is operable to generate a clock signal having an active phase and an inactive phase. A set of monotonic flip-flops are operable to capture a set of incoming data addresses during the active cycle of the clock and to generate therefrom data corresponding to single bits in the addresses that have changed compared to the data addresses received by the set of monotonic flip-flops during an immediately preceding data capture cycle. A set of static flip-flops are operable to capture a set of incoming data addresses during the inactive phase of the clock cycle and to generate set output data therefrom. A decoder operable to process the set output data from the set of static flip-flops and to generate a set of old wordlines corresponding to a set of data addresses in the immediately preceding data capture cycle.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Inventors: Animesh Jain, Nagendra Chandrakar, Sonia Ghosh