Abstract: The embodiments herein provide a Crystalline Strontium Titanate (STO) and a method for deposition of the STO on a silicon substrate. The embodiments herein utilize radio-frequency (RF) magnetron sputtering to grow crystalline pure phase Strontium Titanate SrTiO3 (STO) with single orientation upon a surface of oriented Silicon (Si) substrates followed by annealing at 800° C. for 1 hour in ambient conditions. Furthermore, the embodiments herein completely eliminates the buffer layer which is generally needed beneath the STO thin films, making the deposition of STO films on silicon substrates much more cost-effective than the existing method. Hence a single crystal STO film is directly obtained on the silicon substrate at the end of the process.

Abstract: The embodiments herein provide a system and method for performing accelerated molecular dynamics computer simulations with uncertainty-aware neural networks. The embodiments herein utilize a computational method to simulate the dynamics of atoms in a multi-element system using accelerated molecular dynamics using neural networks (NN) without compromising the accuracy. The formulated method involves simulating the system using ab initio molecular dynamics (AIMD) for a certain number of steps, which are utilized, to train the NN. Further, the trained NN can infer the further steps of the simulation. Here, the uncertainty of the prediction is closely monitored by incorporating uncertainty quantification into NN models. Uncertainty over the threshold indicates the need for more training and hence the usage of AIMD for a few more steps. Therefore, the embodiments herein help in delivering an accurate simulation results at an accelerated speed.

Abstract: The embodiments herein provide lithium iron phosphate (LFP) cathode active materials and a method for deposition of the LFP active materials on an aluminum-foil current collector for lithium-ion (Li-ion) batteries. The embodiments herein utilize an aqueous based LFP precursor slurry made using combustion chemistry, where the LFP precursor slurry is composed of a redox mixture of the nitrates of lithium and iron, dihydrogen ammonium phosphate and glycine in water in the presence of flora-based sodium-carboxy methylcellulose as an organic binder. Furthermore, the thick and transparent precursors slurry is deposited on the aluminum current collector followed by annealing at appropriate pressures and atmospheric conditions. Therefore, the heat liberated in the exothermic reaction of the redox mixture not only assists in the formation of LFP cathode active materials, but also in the incineration of the organic binders and the solvent.

Abstract: The embodiments herein disclose a method and a system for sensor position optimization in an autonomous vehicle. The system and method is configured to receive the weight assigned for each point in the regions of interest around the autonomous vehicle, possible positions of the sensors on the vehicle, and field of view and price of each sensor. The method further calculates a field of view and price of each specification based on the received weights of points in the regions of interest and possible positions of the sensors on the vehicle. The method runs quantum or quantum-inspired variational algorithm for various sensor configurations and the system completes the total number of iterations to generate the final sensor configuration.

Abstract: A method and a system for fabricating superconducting nanowire single photon detector (SNSPD) is disclosed. The superconducting nanowire single photon detector consists of a thin film of superconducting material shaped into a meandering nanowire through nanofabrication processes. The pattern enables the nanowire to cover a wide surface area. The SNSPD is a type of near-infrared single-photon detector based on a current-biased superconducting nanowire. The method includes depositing a plurality of buffer layers on a substrate of a superconducting nanowire single photon detector using a pulsed laser deposition technique. The method further includes designing deposited buffer layer into a desired pattern of nanostrips and depositing a plurality of high temperature superconductor (HTS) on the desired pattern of nanostrips. To obtain the desired pattern, at least one of lithography and/or etching processes is used in the SNSPD.

Abstract: A system and a method for controlling a qubit in a decentralized and distributed manner to obtain a scalable structure of a hybrid quantum-classical architecture is disclosed. The system includes a circuit configured to provide an operation frequency control of qubits in an island representation of a logical qubit island with a plurality of physical qubits along with independent magnetic-field control to each qubit on a hardware substrate. The circuit includes a plurality of micro/nano-scale current-carrying structures in the vicinity of a qubit for controlling and manipulating the qubit using the locally generated variable magnetic field, in turn controlled by a tunable current flowing through the plurality of micro/nano-scale current-carrying structures. The plurality of micro/nano-scale current-carrying structures in conjunction with a fast current control are configured to provide fast switching/tuning of magnetic fields enabling rapid adiabatic passage control of one or more qubits simultaneously.

Abstract: The embodiments herein provide a method and a system for generating and regulating local magnetic field variations required for spin qubit manipulation based on scalable quantum processors using micro-structures in integrated circuits. In an embodiment the system provides an adaptive and independent magnetic-field control to each qubit on a hardware substrate and comprises several micro/nano-scale current-carrying structures near a qubit for controlling and manipulating the qubit using the locally generated variable magnetic field, in-turn controlled by the tunable current flowing through these structures. The current-carrying structures in conjunction with fast current control provides fast switching/tuning of magnetic fields for rapid adiabatic passage control of one or more qubits simultaneously.

Abstract: Disclosed is a system and method for capacity planning based on intelligent feedback and analytics. The system clusters one or more resources (such as virtual machines) based on utilization to identify and group together resources with similar behavior. The system scores an efficiency of each resource based on utilization or characterizing the resource type. The system characterizes the workloads. The system develops a reinforcement learning based agent to help make capacity planning decisions by utilizing the steps of clustering, efficiency scoring and characterization.

Abstract: The embodiments herein disclose a system and method for combinatorial optimization of vehicle routing using simulated annealing on a universal optimization processor. The system characterizes the transport request from a supplier to a customer with its pickup location and delivery location respectively and also records the load volume for the corresponding request. The transport requests are received as an input and the system optimizes route plans for the collection of transport requests based on a simulated annealing. The system defines a route as valid if and only if (when) pickup location precedes the delivery location in route enumeration. Each vehicle is characterized by its maximum capacity value, such that a total volume of loads transported by a vehicle for a given set of delivery services cannot exceed its maximum capacity value. The system generates near-optimal route plan and total distance travelled based on a simulated annealing metaheuristic.

Abstract: A system and method include receiving a resource headroom data of an edge device, receiving resource utilization data of a plurality of applications, and selecting a group of applications from the plurality of applications for installation on the edge device based upon the resource headroom of the edge device. The system and method also include computing a fitness score based upon a suitability of the selected group of applications for the edge device, generating a reward based on the fitness score, and using the reward to refine the selection of the group of selections in subsequent iterations.

Abstract: A reinforcement learning processor specifically configured to train reinforcement learning agents in the AI systems by the way of implementing an application-specific instruction set is disclosed. The application-specific instruction set incorporates ‘Single Instruction Multiple Agents (SIMA)’ instructions. SIMA type instructions are specifically designed to be implemented simultaneously on a plurality of reinforcement learning agents which interact with corresponding reinforcement learning environments. The SIMA type instructions are specifically configured to receive either a reinforcement learning agent ID or a reinforcement learning environment ID as the operand. The reinforcement learning processor is designed for parallelism in reinforcement learning operations. The reinforcement learning processor executing of a plurality of threads associated with an operation or task in parallel.

Abstract: The embodiments herein disclose a system and method for implementing reinforcement learning agents using a reinforcement learning processor. An application-domain specific instruction set (ASI) for implementing reinforcement learning agents and reward functions is created. Further, instructions are created by including at least one of the reinforcement learning agent ID vectors, the reinforcement learning environment ID vectors, and length of vector as an operand. The reinforcement learning agent ID vectors and the reinforcement learning environment ID vectors are pointers to a base address of an operations memory. Further, at least one of said reinforcement learning agent ID vector and reinforcement learning environment ID vector is embedded into operations associated with the decoded instruction. The instructions retrieved by agent ID vector indexed operation are executed using a second processor, and applied onto a group of reinforcement learning agents.

Abstract: A reinforcement learning processor specifically configured to train reinforcement learning agents in the AI systems by the way of implementing an application-specific instruction set is disclosed. The application-specific instruction set incorporates ‘Single Instruction Multiple Agents (SIMA)’ instructions. SIMA type instructions are specifically designed to be implemented simultaneously on a plurality of reinforcement learning agents which interact with corresponding reinforcement learning environments. The SIMA type instructions are specifically configured to receive either a reinforcement learning agent ID or a reinforcement learning environment ID as the operand. The reinforcement learning processor is designed for parallelism in reinforcement learning operations. The reinforcement learning processor executing of a plurality of threads associated with an operation or task in parallel.

Abstract: The embodiments herein discloses a system and method for designing SoC by using a reinforcement learning processor. An SoC specification input is received and a plurality of domains and a plurality of subdomains is created using application specific instruction set to generate chip specific graph library. An interaction is initiated between the reinforcement learning agent and the reinforcement learning environment using the application specific instructions. Each of the SoC sub domains from the plurality of SoC sub domains is mapped to a combination of environment, rewards and actions by a second processor. Further, interaction of a plurality of agents is initiated with the reinforcement learning environment for a predefined number of times and further Q value, V value, R value, and A value is updated in the second memory module. Thereby, an optimal chip architecture for designing SoC is acquired using application-domain specific instruction set (ASI).

Abstract: The embodiments herein disclose a system and method for implementing reinforcement learning agents using a reinforcement learning processor. An application-domain specific instruction set (ASI) for implementing reinforcement learning agents and reward functions is created. Further, instructions are created by including at least one of the reinforcement learning agent ID vectors, the reinforcement learning environment ID vectors, and length of vector as an operand. The reinforcement learning agent ID vectors and the reinforcement learning environment ID vectors are pointers to a base address of an operations memory. Further, at least one of said reinforcement learning agent ID vector and reinforcement learning environment ID vector is embedded into operations associated with the decoded instruction. The instructions retrieved by agent ID vector indexed operation are executed using a second processor, and applied onto a group of reinforcement learning agents.

Abstract: The embodiments herein discloses a system and method for designing SoC by using a reinforcement learning processor. An SoC specification input is received and a plurality of domains and a plurality of subdomains is created using application specific instruction set to generate chip specific graph library. An interaction is initiated between the reinforcement learning agent and the reinforcement learning environ lent using the application specific instructions. Each of the SoC sub domains from the plurality of SoC sub domains is mapped to a combination of environment, rewards and actions by a second processor. Further, interaction of a plurality of agents is initiated with the reinforcement learning environment for a predefined number of times and further Q value, V value, R value, and A value is updated in the second memory module. Thereby, an optimal chip architecture for designing SoC is acquired using application-domain specific instruction set (ASI).

Abstract: A reinforcement learning processor specifically configured to train reinforcement learning agents in the AI systems by the way of implementing an application-specific instruction set is disclosed. The application-specific instruction set incorporates ‘Single Instruction Multiple Agents (SIMA)’ instructions. SIMA type instructions are specifically designed to be implemented simultaneously on a plurality of reinforcement learning agents which interact with corresponding reinforcement learning environments. The SIMA type instructions are specifically configured to receive either a reinforcement learning agent ID or a reinforcement learning environment ID as the operand. The reinforcement learning processor is designed for parallelism in reinforcement learning operations. The reinforcement learning processor executing of a plurality of threads associated with an operation or task in parallel.

Abstract: A reinforcement learning processor specifically configured to train reinforcement learning agents in the AI systems by the way of implementing an application-specific instruction set is disclosed. The application-specific instruction set incorporates ‘Single Instruction Multiple Agents (SIMA)’ instructions. SIMA type instructions are specifically designed to be implemented simultaneously on a plurality of reinforcement learning agents which interact with corresponding reinforcement learning environments. The SIMA type instructions are specifically configured to receive either a reinforcement learning agent ID or a reinforcement learning environment ID as the operand. The reinforcement learning processor is designed for parallelism in reinforcement learning operations. The reinforcement learning processor executing of a plurality of threads associated with an operation or task in parallel.

Abstract: The embodiments herein discloses a system and method for designing SoC by synchronizing a hierarchy of SMDPs. Reinforcement Learning is done either hierarchically in several steps or in a single-step comprising environment, tasks, agents and experiments, to have access to SoC (System on a Chip) related information. The AI agent is configured to learn from the interaction and plan the implementation of a SoC circuit design. Q values generated for each domain and sub domain are stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database. An optimal chip architecture corresponding to a maximum Q value of a top level in the SMDP Q table is acquired and stored in a database for learning and inference. Desired SoC configuration is optimized and generated based on the optimal chip architecture and the generated chip specific graph library.

Abstract: The embodiments herein discloses a system and method for designing SoC using AI and Reinforcement Learning (RL) techniques. Reinforcement Learning is done either hierarchically in several steps or in a single-step comprising environment, tasks, agents and experiments, to have access to SoC (System on a Chip) related information. The AI agent is configured to learn from the interaction and plan the implementation of a SoC circuit design. Q values generated for each domain and sub domain are stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database. An optimal chip architecture corresponding to a maximum Q value of a top level in the SMDP Q table is acquired and stored in a database for learning and inference. Desired SoC configuration is optimized and generated based on the optimal chip architecture and the generated chip specific graph library.