Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

Abstract: A method for optimizing invoice payments according to supplier and buyer controls includes: receiving one or more received data message including invoice data, a buyer identification value, a supplier identification value, and a plurality of buyer optimization priorities, wherein the invoice data is associated with an invoice and includes an invoice amount and due date; identifying a plurality of supplier controls associated with the supplier identification value; identifying one or more buyer preferences associated with the buyer identification value; determining an optimal payment schedule for one or more payment transactions for the invoice based on the invoice data, the buyer optimization priorities, the plurality of supplier controls, and the one or more buyer preferences; transmitting a transmitted data message including the determined optimal payment schedule.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

Abstract: A system and method are disclosed for quality assurance and performance testing of supply chain applications and systems. Embodiments include providing a user interface for receiving a test case file that describes one or more actions to be tested and a properties file that maps one or more elements to one or more values, translating a received test case file and a corresponding properties file into a test case, and executing the test case by identifying the one or more actions identified in the test case and automatically invoking one or more testing components configured to execute a test using the one or more actions, wherein at least one of the one or more testing components is configured execute performance testing, and at least one of the one or more testing components is configured to execute regression testing.

Abstract: Systems and computer-implemented methods are described for modeling card inactivity. For example, hierarchical modeling may be used in which a first level classifier may be trained and validated to predict whether a card will be inactive. For cards predicted to become inactive by the first level classifier, a second level classifier may be trained and validated to predict when the card will become inactive. The first level classifier may include a binary classifier that generates two probabilities that respectively predict that the card will and will not become inactive. The second level classifier may include a multi-class classifier that generates a first probability that the card will become inactive at a first time period (such as one or more months in the future) and a second probability that the card will become inactive at a second time period. The multi-class classifier may generate other probabilities corresponding to other time periods.

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, initiates a failed byte count read operation on the segment of the memory array to determine a failed byte count, and reads metadata stored in a flag byte corresponding to the segment of the memory array concurrently with the failed byte count read operation. The control logic further configures one or more parameters associated with the read operation based on the failed byte count and at least a portion of the metadata read from the flag byte.

Abstract: A system and method are disclosed for quality assurance and performance testing of supply chain applications and systems. Embodiments include providing a user interface for receiving a test case file that describes one or more actions to be tested and a properties file that maps one or more elements to one or more values, translating a received test case file and a corresponding properties file into a test case, and executing the test case by identifying the one or more actions identified in the test case and automatically invoking one or more testing components configured to execute a test using the one or more actions, wherein at least one of the one or more testing components is configured execute performance testing, and at least one of the one or more testing components is configured to execute regression testing.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

Abstract: An example system can include a memory component and a processing device. The memory component can include a group of memory cells. The processing device can be coupled to the memory component. The processing device can be configured to use a first voltage window for a set of memory cells of the group of memory cells during a first time period. The processing device can be configured to determine that an error rate of a sub-set of the set of memory cells is above a threshold error rate. The processing device can be configured to, in response to the determination that the error rate of the sub-set of memory cells is above the threshold error rate, use a second voltage window for the set of memory cells of the group of memory cells during a second time period.

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.

Abstract: A first program pass of a multi-pass program operation is caused to be performed at a memory array. A first program voltage is applied to a wordline of a block of the memory array to program one or more memory cells during the first program pass. Subsequent to the first program pass of the multi-pass program operation, a pre-read operation is caused to be performed to read data corresponding to the first program pass and from the one or more memory cells. Whether a shift of a threshold voltage corresponding to the one or more memory cells satisfies a condition related to a threshold voltage change is determined based on the pre-read operation. Responsive to determining that the shift of the threshold voltage satisfies the condition, an updated second program voltage of a second program pass of the multi-pass program operation is determined.

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

Abstract: A diagnostics and prediction system including a cloud system that continuously collects operating parameters from each of a number of environmental sensors and provides access to this data by a plurality of processing applications including (1) a predictive modeling system including (a) a health prediction system, (b) a sensor false alarm prediction system, (c) a zone false alarm prediction system and (d) a reporting system, (2) a system that diagnoses and predicts environmental hazardous areas and clusters areas based upon concentrations of CO in the site or building; and (3) a battery prediction system that predicts a battery life for the sensor.

Abstract: Embodiments provide methods and systems for identifying a re-routed transaction. Method performed by processor includes retrieving a plurality of transaction windows from a transaction database. Each transaction window includes a transaction declined under a restricted MCC. The method includes accessing a plurality of features associated with each transaction of each transaction window from the transaction database. The method includes predicting an output dataset of a plurality of reconstructed transaction windows based on feeding the input dataset to a trained neural network model. The method includes computing a corresponding reconstruction loss value for each transaction of each transaction window. The method includes comparing the corresponding reconstruction loss value for each transaction with a pre-determined threshold value.

Abstract: The disclosure relates to AI-based machine-learning and natural language modeling to identify semantic similarities between sets of content having natural language text. For example, a system may generate a relevance classification that indicates whether content such as articles are non-specifically relevant to charities without identifying a particular charity. If the content is non-specifically relevant to charities, the system may apply a natural language model to generate sentence embeddings based on the content and determine a level similarity between the sentence embeddings and a query embedding generated from a charity query. The charity query may itself be generated from a full description of the charity through an encoder-decoder architecture with reinforcement learning.

Abstract: A method and apparatus for determining a unique wake word for devices within an incident. One system includes an electronic computing device comprising a transceiver and an electronic processor communicatively coupled to the transceiver. The electronic processor is configured to receive a notification indicative of an occurrence of an incident and one or more communication devices present at the incident, determine contextual information associated with the incident and the one or more communication devices, and identify one or more wake words based on the contextual information. The electronic processor is further configured to determine a phonetic distance for each pair of wake words included in the one or more wake words, and select a unique wake word from the one or more wake words for each communication device of the one or more communication devices based on the determined phonetic distance.

Abstract: A processing device, operatively coupled with a memory device, is configured to identify a temperature related to a memory device of a plurality of memory devices; to determine, whether the temperature satisfies a threshold temperature condition; responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, to identify an entry associated with the memory device from a plurality of entries in a data structure, wherein each entry of the plurality of entries corresponds to one of the plurality of memory devices; to determine a parameter value associated with the memory device from the entry, wherein the parameter value is for a programming operation to store data at the memory device; to adjust the parameter value associated with the memory device to generate an adjusted parameter value; and to store the adjusted parameter value in the entry of the data structure.