Patents by Inventor Nagesh Shirali
Nagesh Shirali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953824Abstract: Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.Type: GrantFiled: May 16, 2023Date of Patent: April 9, 2024Assignee: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Patent number: 11921420Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information, calculating a mask 2D (M2D) effect from the mask exposure information, and determining the M3D effect from the M2D effect. Determining the M3D effect may include determining the VSA, such as by using a neural network. Embodiments may include determining a dose margin from mask exposure information; calculating a VSA using the dose margin; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.Type: GrantFiled: January 20, 2023Date of Patent: March 5, 2024Assignee: D2S, Inc.Inventors: Akira Fujimura, Nagesh Shirali, Ajay Baranwal
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Patent number: 11886166Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.Type: GrantFiled: February 14, 2023Date of Patent: January 30, 2024Assignee: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
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Publication number: 20230386784Abstract: Methods and systems for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose may be calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.Type: ApplicationFiled: August 3, 2023Publication date: November 30, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
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Patent number: 11783110Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.Type: GrantFiled: July 30, 2021Date of Patent: October 10, 2023Assignee: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Publication number: 20230288796Abstract: Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.Type: ApplicationFiled: May 16, 2023Publication date: September 14, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Publication number: 20230289510Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include determining an initial mask pattern from a desired pattern for a substrate; calculating a first substrate pattern from the initial mask pattern; determining an initial set of VSB shots that will form the initial mask pattern; calculating a simulated mask pattern from the initial set of VSB shots; calculating a second substrate pattern from the simulated mask pattern; and adjusting the initial set of VSB shots, wherein the adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.Type: ApplicationFiled: May 16, 2023Publication date: September 14, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Patent number: 11756765Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area of the desired shape based on an original set of exposure information. A backscatter for a sub area is calculated, based on the original set of exposure information. Dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A pre-PEC maximum dose is determined for the local pattern density, based on a pre-determined target post-PEC maximum dose. The original set of exposure information is modified with the pre-PEC maximum dose and the increased dosage of the at least one pixel in the sub area to create a modified set of exposure information.Type: GrantFiled: June 17, 2021Date of Patent: September 12, 2023Assignee: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
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Publication number: 20230244137Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information, calculating a mask 2D (M2D) effect from the mask exposure information, and determining the M3D effect from the M2D effect. Determining the M3D effect may include determining the VSA, such as by using a neural network. Embodiments may include determining a dose margin from mask exposure information; calculating a VSA using the dose margin; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.Type: ApplicationFiled: January 20, 2023Publication date: August 3, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, Nagesh Shirali, Ajay Baranwal
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Patent number: 11693306Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.Type: GrantFiled: July 30, 2021Date of Patent: July 4, 2023Assignee: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Publication number: 20230205177Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.Type: ApplicationFiled: February 14, 2023Publication date: June 29, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
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Publication number: 20230186009Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.Type: ApplicationFiled: August 16, 2022Publication date: June 15, 2023Inventors: Akira Fujimura, Nagesh Shirali, Donald Oriordan
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Publication number: 20230124768Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose is calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
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Publication number: 20230092665Abstract: A method of some embodiments receives an initial first physical design of a circuit. The method uses a machine-trained network to generate a second physical design that is a prediction of how the first physical design will look at a subsequent manufacturing stage. The method then uses the second physical design to modify the first physical design. Examples of such modifications include modifying a set of one or more routes in the first physical design and/or modifying a set of placement locations of a set of one or more sub-circuits or circuit components defined in the first physical design.Type: ApplicationFiled: September 21, 2022Publication date: March 23, 2023Inventors: Akira Fujimura, Nagesh Shirali, Donald Oriordan
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Patent number: 11604451Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information. A dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A modified set of exposure information is output, including the increased dosage of the at least one pixel in the sub area.Type: GrantFiled: March 24, 2021Date of Patent: March 14, 2023Assignee: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
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Patent number: 11592802Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. A backscatter is calculated for the area of the pattern based on the exposure information. An artificial background dose is determined for the area. The artificial background dose comprises additional exposure information and is combined with the original set of exposure information creating a modified set of exposure information. A system for exposing a pattern in an area on a surface using a charged particle beam lithography is also disclosed.Type: GrantFiled: December 28, 2020Date of Patent: February 28, 2023Assignee: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, William E. Guthrie, Ryan Pearman
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Publication number: 20230035090Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Publication number: 20230034170Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Publication number: 20230032510Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.Type: ApplicationFiled: August 16, 2022Publication date: February 2, 2023Inventors: Akira Fujimura, Nagesh Shirali, Donald Oriordan
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Publication number: 20230027655Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.Type: ApplicationFiled: July 22, 2022Publication date: January 26, 2023Inventors: Akira Fujimura, Nagesh Shirali, Donald Oriordan