Abstract: An active pixel sensor a plurality of sensor pixels disposed in a row, a plurality of sensor pixels in a column, and steering circuitry coupled to each of the sensor pixels. Each of the sensor pixels includes a first pixel circuit, and a second pixel circuit. For each of the sensor pixels, the steering circuitry includes a first switch, a second switch, a third switch, and a fourth switch. The first switch and the second switch are connected in series to route an input signal to the first pixel circuit. The third switch and a fourth switch are connected in parallel to route the input signal to the second pixel circuit.

Abstract: An active pixel sensor a plurality of sensor pixels disposed in a row, a plurality of sensor pixels in a column, and steering circuitry coupled to each of the sensor pixels. Each of the sensor pixels includes a first pixel circuit, and a second pixel circuit. For each of the sensor pixels, the steering circuitry includes a first switch, a second switch, a third switch, and a fourth switch. The first switch and the second switch are connected in series to route an input signal to the first pixel circuit. The third switch and a fourth switch are connected in parallel to route the input signal to the second pixel circuit.

Abstract: A photon counting system includes a photon sensor, a charge-sensitive amplifier (CSA) and an analog-to-digital converter (ADC). The CSA is configured to convert photon energy detected by the photon sensor to voltage pulses. The ADC is configured to digitize the voltage pulses generated by the CSA. The ADC includes successive approximation circuitry. The successive approximation circuitry includes an N-bit digital-to-analog converter (DAC), an N-bit successive approximation register (SAR), a plurality of N-bit registers, and a multiplexer configured to selectively route outputs of the SAR and outputs of the N-bit registers to the DAC for conversion to an analog signal.

Abstract: A circuit includes a charge sensitive amplifier (CSA) that includes an input to receive current from a photon sensor and generates an output signal that represents photons received by the sensor and dark current of the sensor. A control circuit generates a compensation signal to offset the dark current from the photon sensor at the input of the CSA. The control circuit couples feedback from the CSA to enable the compensation signal if the photon current received from the sensor is below a predetermined threshold. The control circuit decouples the feedback from the CSA to disable the compensation signal if the photon current received from the sensor is above the predetermined threshold.

Abstract: A photon counting system includes a photon sensor, a charge-sensitive amplifier (CSA) and an analog-to-digital converter (ADC). The CSA is configured to convert photon energy detected by the photon sensor to voltage pulses. The ADC is configured to digitize the voltage pulses generated by the CSA. The ADC includes successive approximation circuitry. The successive approximation circuitry includes an N-bit digital-to-analog converter (DAC), an N-bit successive approximation register (SAR), a plurality of N-bit registers, and a multiplexer configured to selectively route outputs of the SAR and outputs of the N-bit registers to the DAC for conversion to an analog signal.

Abstract: The disclosure provides a circuit that includes a charge sensitive amplifier (CSA) that generates an integrated signal in response to a current signal. An active comparator is coupled to the CSA. The active comparator receives the integrated signal and a primary reference voltage signal, and generates an event detect signal. A first delay element is coupled to the active comparator and provides a fixed delay to the event detect signal to generate a convert signal. A discriminator system is coupled to the CSA. The discriminator system samples the integrated signal when activated by the convert signal.

Abstract: The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A pixel switch is coupled to the photodiode. An operational amplifier is coupled to the photodiode through the pixel switch. A feedback capacitor and a reset switch are coupled between a first input port and an output port of the operational amplifier. A switched resistor network is coupled to the output port of the operational amplifier. A first switched capacitor network is coupled to the switched resistor network and samples a reset voltage. A second switched capacitor network is coupled to the switched resistor network and samples a signal voltage. A subtractor receives the reset voltage and the signal voltage, and generates a sample voltage. The second switched network comprises two or more capacitors.

Abstract: A photon counting system includes a photon sensor and pixel circuitry. The pixel circuitry includes a charge sensitive amplifier (CSA), an analog to digital converter (ADC), an event detector, and a coincidence detector. The CSA is configured to convert photon energy detected by the photon sensor to a voltage pulse. The ADC is coupled to an output of the CSA. The ADC is configured to digitize the voltage pulses generated by the CSA. The event detector is configured to determine whether output voltage of the CSA exceeds an event threshold voltage, and to trigger the ADC to digitize the output voltage based on the output voltage exceeding the event threshold voltage. The coincidence detector is configured to determine whether the output voltage of the CSA exceeds a coincidence threshold voltage, and to trigger the ADC to digitize the output voltage based on the output voltage exceeding the coincidence threshold voltage.

Abstract: The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A pixel switch is coupled to the photodiode. An operational amplifier is coupled to the photodiode through the pixel switch. A feedback capacitor and a reset switch are coupled between a first input port and an output port of the operational amplifier. A switched resistor network is coupled to the output port of the operational amplifier. A first switched capacitor network is coupled to the switched resistor network and samples a reset voltage. A second switched capacitor network is coupled to the switched resistor network and samples a signal voltage. A subtractor receives the reset voltage and the signal voltage, and generates a sample voltage. The second switched network comprises two or more capacitors.

Abstract: A circuit includes a charge sensitive amplifier (CSA) that includes an input to receive current from a photon sensor and generates an output signal that represents photons received by the sensor and dark current of the sensor. A control circuit generates a compensation signal to offset the dark current from the photon sensor at the input of the CSA. The control circuit couples feedback from the CSA to enable the compensation signal if the photon current received from the sensor is below a predetermined threshold. The control circuit decouples the feedback from the CSA to disable the compensation signal if the photon current received from the sensor is above the predetermined threshold.

Abstract: The disclosure provides a circuit that includes a charge sensitive amplifier (CSA) that generates an integrated signal in response to a current signal. An active comparator is coupled to the CSA. The active comparator receives the integrated signal and a primary reference voltage signal, and generates an event detect signal. A first delay element is coupled to the active comparator and provides a fixed delay to the event detect signal to generate a convert signal. A discriminator system is coupled to the CSA. The discriminator system samples the integrated signal when activated by the convert signal.

Abstract: Charge to voltage conversion integrator circuitry for data acquisition front-end and other applications to provide a single-ended up a voltage using an input bias capacitance and a switching circuit to selectively place an input transistor in a negative feedback configuration in a first mode to charge the input bias capacitance to a calibration voltage for compensating integrator amplifier bias circuitry, with the switching circuit connecting an input node and the input bias capacitance in a second mode to integrate the input current signal across a feedback capacitance to provide a single-ended output voltage with the input bias capacitance maintaining a zero voltage at the input node.

Abstract: Charge to voltage conversion integrator circuitry for data acquisition front-end and other applications to provide a single-ended up a voltage using an input bias capacitance and a switching circuit to selectively place an input transistor in a negative feedback configuration in a first mode to charge the input bias capacitance to a calibration voltage for compensating integrator amplifier bias circuitry, with the switching circuit connecting an input node and the input bias capacitance in a second mode to integrate the input current signal across a feedback capacitance to provide a single-ended output voltage with the input bias capacitance maintaining a zero voltage at the input node.

Abstract: Output voltage of a charge-to-voltage converter used in an image sensing system is compared with one or more thresholds to determine if the output voltage exceeds predetermined threshold levels. If the output voltage exceeds one or more of the threshold levels, the input terminal of the charge-to-voltage converter is connected to a reference voltage to prevent the charge-to-voltage converter from saturating. Problems that could be caused due to overload of the voltage-to-charge converter are obviated. In an embodiment, the charge-to-voltage converter is implemented by an operational amplifier (OPAMP). A pair of comparators compares the output of the OPAMP with corresponding threshold voltages. The result of the comparison is used to generate a signal for connecting the input of the OPAMP to the reference voltage, thereby preventing saturation of the OPAMP.

Abstract: The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A pixel switch is coupled to the photodiode. An operational amplifier is coupled to the photodiode through the pixel switch. A feedback capacitor and a reset switch are coupled between a first input port and an output port of the operational amplifier. A switched resistor network is coupled to the output port of the operational amplifier. A first switched capacitor network is coupled to the switched resistor network and samples a reset voltage. A second switched capacitor network is coupled to the switched resistor network and samples a signal voltage. A subtractor receives the reset voltage and the signal voltage, and generates a sample voltage. The second switched network comprises two or more capacitors.

Abstract: Output voltage of a charge-to-voltage converter used in an image sensing system is compared with one or more thresholds to determine if the output voltage exceeds predetermined threshold levels. If the output voltage exceeds one or more of the threshold levels, the input terminal of the charge-to-voltage converter is connected to a reference voltage to prevent the charge-to-voltage converter from saturating. Problems that could be caused due to overload of the voltage-to-charge converter are obviated. In an embodiment, the charge-to-voltage converter is implemented by an operational amplifier (OPAMP). A pair of comparators compares the output of the OPAMP with corresponding threshold voltages. The result of the comparison is used to generate a signal for connecting the input of the OPAMP to the reference voltage, thereby preventing saturation of the OPAMP.

Abstract: A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.

Abstract: A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.