Patents by Inventor Nagesh Vodrahalli
Nagesh Vodrahalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145424Abstract: A storage device includes a substrate of a memory package that includes a first pin pad, a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel, and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.Type: ApplicationFiled: July 19, 2023Publication date: May 2, 2024Inventors: John Contreras, Nagesh Vodrahalli, Md. Sayed Mobin
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Publication number: 20240079318Abstract: A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Md. Sayed Mobin, Nagesh Vodrahalli, Pranav Balachander, Narayanan Terizhandur V
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Publication number: 20230395438Abstract: A semiconductor device includes a die stack having dies selected into the stack based on their thicknesses. After the dies are formed on a wafer and thinned, a metrology tool is used to determine the thicknesses of the dies in the wafer. These thicknesses are stored in a known thickness die (KTD) map, along with other information such as their standard and average deviations and their classification into a binning class. In one example, dies which have been classified into bin 1 (having an optimal thickness) are selected to provide a high capacity highly reliable semiconductor device. In a further example, dies of different bins are mixed and matched to provide a uniform, highly controlled overall die stack height.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Nagesh Vodrahalli, Chih Yang Li, Xuyi Yang, Cong Zhang
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Patent number: 11770982Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.Type: GrantFiled: August 9, 2021Date of Patent: September 26, 2023Assignee: Rigetti & Co, LLCInventors: Jayss Daniel Marshall, Chih-Yang Li, Biswajit Sur, Nagesh Vodrahalli, Mehrnoosh Vahidpour, William Austin O'Brien, IV, Andrew Joseph Bestwick, Chad Tyler Rigetti, James Russell Renzas
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Patent number: 11444062Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.Type: GrantFiled: April 29, 2021Date of Patent: September 13, 2022Assignee: SanDisk Technologies LLCInventor: Nagesh Vodrahalli
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Patent number: 11121301Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.Type: GrantFiled: June 19, 2018Date of Patent: September 14, 2021Assignee: Rigetti & Co, Inc.Inventors: Jayss Daniel Marshall, Chih-Yang Li, Biswajit Sur, Nagesh Vodrahalli, Mehrnoosh Vahidpour, William Austin O'Brien, IV, Andrew Joseph Bestwick, Chad Tyler Rigetti, James Russell Renzas
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Patent number: 11094674Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.Type: GrantFiled: March 12, 2020Date of Patent: August 17, 2021Assignee: SanDisk Technologies LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Rama Shukla
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Publication number: 20210249385Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Applicant: SANDISK TECHNOLOGIES LLCInventor: Nagesh Vodrahalli
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Patent number: 11011500Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.Type: GrantFiled: March 12, 2020Date of Patent: May 18, 2021Assignee: SanDisk Technologies LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Chih Yang Li, Srinivasan Sivaram, Rama Shukla
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Patent number: 11004829Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.Type: GrantFiled: October 7, 2019Date of Patent: May 11, 2021Assignee: SanDisk Technologies LLCInventor: Nagesh Vodrahalli
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Patent number: 10985308Abstract: In a general aspect, an integrated microwave circuit is disclosed for processing quantum information. The integrated microwave circuit includes a substrate having a first surface and a second surface opposite the first surface. The substrate is formed of a silicon oxide material having a loss tangent no greater than 1×10?5 at cryogenic temperatures at or below 120 K. The integrated microwave circuit also includes qubit circuitry disposed on the first surface that includes a Josephson junction. A ground plane is disposed on the first surface or the second surface. In some variations, the silicon oxide material is fused silica. In other variations, the silicon oxide material is crystalline quartz.Type: GrantFiled: January 13, 2020Date of Patent: April 20, 2021Assignee: Rigetti & Co, Inc.Inventor: Nagesh Vodrahalli
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Publication number: 20210104494Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.Type: ApplicationFiled: March 12, 2020Publication date: April 8, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Rama Shukla
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Publication number: 20210104495Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.Type: ApplicationFiled: March 12, 2020Publication date: April 8, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Chih Yang Li, Srinivasan Sivaram, Rama Shukla
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Publication number: 20210104493Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.Type: ApplicationFiled: October 7, 2019Publication date: April 8, 2021Applicant: SANDISK TECHNOLOGIES LLCInventor: Nagesh Vodrahalli
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Patent number: 10811392Abstract: A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.Type: GrantFiled: February 27, 2019Date of Patent: October 20, 2020Assignee: Western Digital Technologies, Inc.Inventors: Toshiki Hirano, Vipin Ayanoor-Vitikkate, Nagesh Vodrahalli
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Publication number: 20200273844Abstract: A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Toshiki Hirano, Vipin Ayanoor-Vitikkate, Nagesh Vodrahalli
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Patent number: 10535809Abstract: In a general aspect, an integrated microwave circuit is disclosed for processing quantum information. The integrated microwave circuit includes a substrate having a first surface and a second surface opposite the first surface. The substrate is formed of a silicon oxide material having a loss tangent no greater than 1×10?5 at cryogenic temperatures at or below 120 K. The integrated microwave circuit also includes qubit circuitry disposed on the first surface that includes a Josephson junction. A ground plane is disposed on the first surface or the second surface. In some variations, the silicon oxide material is fused silica. In other variations, the silicon oxide material is crystalline quartz.Type: GrantFiled: August 29, 2018Date of Patent: January 14, 2020Assignee: Rigetti & Co, Inc.Inventor: Nagesh Vodrahalli
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Patent number: 9870959Abstract: Techniques for electrically testing a flip-chip assembly during its manufacture include a flip-chip assembly having an integrated circuit (IC) die and an IC package substrate. The IC package substrate is placed on a substrate part holder that includes test sockets and heating elements. The IC die is then placed on the placed IC package substrate. The placed IC die and IC package substrate are aligned such that conductive contacts are formed from conductive bumps and pads deposited on the surface of the IC die and IC package substrate. While the bumps and pads are in conductive contact, but prior to attachment, the flip-chip assembly is electrically tested. If the flip-chip assembly passes electrical testing, the conductive contacts may be attached by the heating elements on the substrate part holder, such as in a solder reflow process when the bumps are made from solder.Type: GrantFiled: October 12, 2012Date of Patent: January 16, 2018Assignee: ALTERA CORPORATIONInventor: Nagesh Vodrahalli
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Patent number: 9201097Abstract: Techniques for electrically testing an integrated circuit (IC) die with a partially completed and validated module (module) include providing an IC die to be tested on an IC package substrate of a validated test module, the positioned IC die and the module forming a multi-die flip-chip test assembly, and without attaching the interconnection bumps of the IC die to the package pads of the module, electrically testing the multi-die flip-chip test assembly. The method may further involve, responsive to the multi-die flip-chip test assembly passing electrical testing positioning the IC die on a production IC package substrate and attaching the IC die to the production IC package substrate. Corresponding apparatus and systems can also be used to perform the technique.Type: GrantFiled: October 12, 2012Date of Patent: December 1, 2015Assignee: Altera CorporationInventor: Nagesh Vodrahalli
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Patent number: 9040348Abstract: A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.Type: GrantFiled: September 7, 2012Date of Patent: May 26, 2015Assignee: Altera CorporationInventors: Nagesh Vodrahalli, Jon M. Long