Patents by Inventor Nagi Aboulenein

Nagi Aboulenein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10621094
    Abstract: An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Zhe Wang, Zeshan A. Chishti, Nagi Aboulenein
  • Patent number: 10516439
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
  • Patent number: 10482947
    Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Uksong Kang, Nagi Aboulenein
  • Publication number: 20190332469
    Abstract: An in-band error correcting code (ECC) module intercepts input/output (I/O) operations directed to a memory. The in-band ECC module determines whether the I/O is directed to data that needs to be protected against error. In response to determining that the I/O is directed to data that needs to be protected against error, the in-band ECC module directs a memory controller to store or access ECC data corresponding to the data in a first preassigned area of the memory, and to store or access the data in a second preassigned area of the memory.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 31, 2019
    Inventors: Amir A. RADJAI, Nagi ABOULENEIN, Steve L. GEIGER, Satyajit A. JADHAV, Bezan J. KAPADIA, Vivek KOZHIKKOTTU, Rashmi LAKKUR SUBRAMANYAM, Srithar RAMESH, James M. SHEHADI, Jason D. VAN DYKEN
  • Publication number: 20190102314
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a workload characteristic for a tag cache, and adjust a power parameter for the tag cache based on the workload characteristic. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Zhe Wang, Zeshan Chishti, Nagi Aboulenein, Zvika Greenfield
  • Publication number: 20190004952
    Abstract: An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Zhe Wang, Zeshan A. Chishti, Nagi Aboulenein
  • Publication number: 20180254079
    Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 6, 2018
    Inventors: Christopher E. COX, Uksong KANG, Nagi ABOULENEIN
  • Patent number: 9940984
    Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Nagi Aboulenein, Jayapratap Bharathan
  • Publication number: 20180090185
    Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: MD Altaf HOSSAIN, Nagi ABOULENEIN, Jayapratap BHARATHAN
  • Patent number: 9851771
    Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Lawrence A Cooper, Justin J Song, Xiuting C Man, Nagi Aboulenein, Christopher E Cox, Rebecca Z Loop
  • Publication number: 20170359099
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Application
    Filed: August 1, 2017
    Publication date: December 14, 2017
    Applicant: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
  • Patent number: 9722663
    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn, Christopher P. Mozak, Nagi Aboulenein, James M. Shehadi
  • Patent number: 9514047
    Abstract: In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Daniel Greenspan, Yoav Lossin, Blaise Fanning, Nagi Aboulenein, Marc Torrant
  • Publication number: 20160179666
    Abstract: In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Daniel Greenspan, Yoav Lossin, Blaise Fanning, Nagi Aboulenein, Marc Torrant
  • Patent number: 9268724
    Abstract: Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: February 23, 2016
    Assignee: INTEL CORPORATION
    Inventors: Md Altaf Hossain, Kevin J. Doran, Nagi Aboulenein
  • Publication number: 20150185797
    Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: Lawrence A. Cooper, Justin J. Song, Xiuting C. Man, Nagi Aboulenein, Christopher E. Cox, Rebecca Z. Loop
  • Patent number: 8924651
    Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Perry P. Tang, Hemant G. Rotithor, Ryan L. Carlson, Nagi Aboulenein
  • Publication number: 20140317343
    Abstract: Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
    Type: Application
    Filed: February 17, 2014
    Publication date: October 23, 2014
    Inventors: Md Altaf Hossain, Kevin J. Doran, Nagi Aboulenein
  • Publication number: 20140136795
    Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.
    Type: Application
    Filed: April 16, 2013
    Publication date: May 15, 2014
    Inventors: PERRY P. TANG, HEMANT G. ROTITHOR, RYAN L. CARLSON, NAGI ABOULENEIN
  • Patent number: 8683096
    Abstract: Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Kevin J. Doran, Nagi Aboulenein