Abstract: A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or more failed hold-up capacitors, the controller is configured to reallocate the write buffers of the write cache for use in one or more subsequent write operations.

Abstract: Disclosed are systems and methods detecting and isolating faulty hold-up capacitors and performing corrective actions for a data storage device. A hardware circuit is coupled to a micro-controller and non-volatile memory dies. The method includes, at the hardware circuit: providing a back-up power for the non-volatile memory dies and the micro-controller; and detecting whether a hold-up capacitor of the hardware circuit is faulty and isolating the hold-up capacitor in accordance with a detection that the hold-up capacitor is faulty. The method also includes, at the micro-controller: obtaining a status of an interface coupled to the hardware circuit; determining a status of the hardware circuit based on the status of the interface; and performing a corrective action for the data storage device in accordance with a determination that the status of hardware circuit corresponds to one or more faulty hold-up capacitors.

Abstract: A storage system suspends an ongoing program operation to execute a read command. There is a limit on the number of times the storage system can suspend the program operation, and latencies occur for read commands that are received after the limit has been reached. To improve read quality of service, a blackout window is established that prevents the storage system from suspending the program operation for a period of time after the program operation resumes. The period of time can be chosen such that program suspensions are evenly distributed over the course of the program operation.

Abstract: A storage system suspends an ongoing program operation to execute a read command. There is a limit on the number of times the storage system can suspend the program operation, and latencies occur for read commands that are received after the limit has been reached. To improve read quality of service, a blackout window is established that prevents the storage system from suspending the program operation for a period of time after the program operation resumes. The period of time can be chosen such that program suspensions are evenly distributed over the course of the program operation.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a command from a device to perform a write operation at the non-volatile memory. The command indicates a plurality of logical addresses, data associated with the plurality of logical addresses, and a number of write operations associated with the command.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a command from a device to perform a write operation at the non-volatile memory. The command indicates a plurality of logical addresses, data associated with the plurality of logical addresses, and a number of write operations associated with the command.

Abstract: Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data.

Abstract: A memory system or flash memory device may include a linking or grouping of blocks that are used for dual writing. In particular, meta-blocks in the memory may be linked in such a way that enables a data transfer to simultaneously occur in two meta-blocks. The dual versions of the programming may be used for error correction. If there is a failure or write error in one of the meta-blocks, then the data from the other meta-block may be used. If there is no failure then the secondary meta-block may be erased.

Abstract: Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data.

Abstract: A memory system or flash memory device may include a linking or grouping of blocks that are used for dual writing. In particular, meta-blocks in the memory may be linked in such a way that enables a data transfer to simultaneously occur in two meta-blocks. The dual versions of the programming may be used for error correction. If there is a failure or write error in one of the meta-blocks, then the data from the other meta-block may be used. If there is no failure then the secondary meta-block may be erased.