Patents by Inventor Nahir Sarmicanic

Nahir Sarmicanic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sub-blocks and meta pages for mapping table rebuild
    Patent number: 9823863
    Abstract: Data associated with logical addresses are received where the data is to be stored on a plurality of solid state storage dies and each of the plurality of solid state storage dies is independently accessible. Metadata is generated that includes the logical addresses where the metadata and the data sum to an amount of information that is less than a maximum amount of information that can be written to the plurality of solid state storage dies in a single write operation. The metadata and the data are stored in the plurality of solid state storage dies.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Hong Lu, Nahir Sarmicanic, Suneel Kumar Indupuru