Abstract: A gate signal masking circuit includes a first switching element including a control electrode connected to a masking control node, a first electrode connected to a first node and a second electrode connected to a control node, a second switching element including a control electrode connected to a second node, a first electrode receiving a first power and a second electrode connected to an intermediate node, a third switching element receiving an enable signal and connected to the intermediate node and a second intermediate node, a fourth switching element receiving the enable signal and connected to the second intermediate node and a third intermediate node, a fifth switching element connected to a third node and the third intermediate node and receiving a second power and a floating switching element receiving a floating control signal and connected to the masking control node and the third intermediate node.

Abstract: A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k-1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

Abstract: A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode connected to a second node, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode connected to the second node, an electrode connected to the fifth node and another electrode receiving a power.

Abstract: A display device includes: a first auxiliary insulating layer through which an opening is defined; a second auxiliary insulating layer on the first auxiliary insulating layer; a pixel definition layer on the second auxiliary insulating layer and having a pixel opening defined therethrough; a first auxiliary electrode having at least a portion in the opening; a second auxiliary electrode having at least a portion in the opening, the second auxiliary electrode comprising a second-first portion on the first auxiliary electrode and a second-second portion comprising a first surface that forms a first angle with an upper surface of the first auxiliary electrode and is spaced apart from the upper surface of the first auxiliary electrode; a first electrode having a portion in the pixel opening; and a second electrode on the first electrode and electrically connected to the first auxiliary electrode.

Abstract: A gate driver includes a control circuit which controls a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, a the second control clock signal, a carry output circuit which generates a carry signal in response to voltages of the first control node and the second control node, an enable node control circuit controlling a voltage of an enable node in response to the carry signal, an enable signal, and an inverted enable signal, a masking circuit which controls a voltage of a first intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the enable node, and a gate output circuit which outputs a gate signal in response to the carry signal, the voltage of the first intermediate node, and an output clock signal.

Abstract: A display apparatus includes a display panel, a data driving circuit and a gate driving circuit. The display panel displays an image and includes a plurality of pixels. The data driving circuit applies a data voltage to a data line of the display panel. The gate driving circuit applies a gate output signal to a gate line of the display panel. The gate driving circuit is disposed between opening portions in a display area of the display panel. The gate driving circuit includes a normal stage column extending in a pixel column direction of the display panel and including a plurality of normal stages and a dummy stage column disposed adjacent to an end portion of the normal stage column in a pixel row direction and including a plurality of dummy stages.

Abstract: Provided is a display apparatus in which an area of a dead space is significantly reduced, the display apparatus including a first scan line extending in a first direction, a second scan line spaced apart from the first scan line and extending in the first direction, a first pixel set disposed between the first scan line and the second scan line, the first pixel set including a 1-1st pixel including n sub-pixels and a 1-2nd pixel including n sub-pixels, and n first data lines spaced apart from each other, disposed between the 1-1st pixel and the 1-2nd pixel in a plan view, extending in a second direction crossing the first direction, and electrically connected to the 1-1st pixel and the 1-2nd pixel.

Abstract: A display device according to an embodiment may include a first sub-display panel and a second sub-display panel adjacent to the first sub-display panel in a first direction. The first sub-display panel may include a first pixel adjacent to the second sub-display panel and a first ground line disposed between the first pixel and the second sub-display panel and extending in a second direction crossing the first direction. The second sub-display panel may include a second pixel adjacent to the first sub-display panel and a second ground line disposed between the second pixel and the first sub-display panel and extending in the second direction.

Abstract: Provided is a display apparatus in which an area of a dead space is significantly reduced, the display apparatus including a first scan line extending in a first direction, a second scan line spaced apart from the first scan line and extending in the first direction, a first pixel set disposed between the first scan line and the second scan line, the first pixel set including a 1-1st pixel including n sub-pixels and a 1-2nd pixel including n sub-pixels, and n first data lines spaced apart from each other, disposed between the 1-1st pixel and the 1-2nd pixel in a plan view, extending in a second direction crossing the first direction, and electrically connected to the 1-1st pixel and the 1-2nd pixel.

Abstract: A tiling display device includes a first display panel and a second display panel that is spaced apart from the first display panel by a horizontal tiling interval. The first display panel includes first to (n)-th pixel columns, and the second display panel includes first to (m)-th pixel columns. A first distance between the (n)-th pixel column of the first display panel and the first pixel column of the second display panel is less than a second distance between a (n?1)-th pixel column of the first display panel and the (n)-th pixel column of the first display panel.

Abstract: Provided is a tiled display device including a first sub-display panel on which a plurality of unit pixels is formed, and a second sub-display panel on which a plurality of unit pixels is formed, and located adjacent to the first sub-display panel, wherein each of the unit pixels includes a display element for emitting colored light, and a plurality of sub-pixels having a pixel circuit for driving the display element, and wherein an arrangement order of sub-pixels in the unit pixels corresponding to a current row, and an arrangement order of the sub-pixels in the unit pixels corresponding to a previous row or a next row, are different from each other.

Abstract: A display device includes a tiled display structure including a first display panel, a second display panel adjacent to a first side of the first display panel, a third display panel adjacent to a second side of the first display panel, and a fourth display panel adjacent to a first side of the third display panel and a first side of the second display panel. Each of the first to fourth display panels includes a display area and a pad area, and each of the first to fourth display panels includes a plurality of pixels in the display area. Each of the pixels includes at least two sub-pixels. When viewed in a plan view of the tiled display structure, the at least two sub-pixels included in each of the pixels are repeatedly arranged in a row direction and a column direction on a plane of the tiled display structure.

Abstract: A display device includes a tiled display structure including a first display panel, a second display panel adjacent to a first side of the first display panel, a third display panel adjacent to a second side of the first display panel, and a fourth display panel adjacent to a first side of the third display panel and a first side of the second display panel. Each of the first to fourth display panels includes a display area and a pad area, and each of the first to fourth display panels includes a plurality of pixels in the display area. Each of the pixels includes at least two sub-pixels. When viewed in a plan view of the tiled display structure, the at least two sub-pixels included in each of the pixels are repeatedly arranged in a row direction and a column direction on a plane of the tiled display structure.

Abstract: Provided is a display apparatus in which an area of a dead space is significantly reduced, the display apparatus including a first scan line extending in a first direction, a second scan line spaced apart from the first scan line and extending in the first direction, a first pixel set disposed between the first scan line and the second scan line, the first pixel set including a 1-1st pixel including n sub-pixels and a 1-2nd pixel including n sub-pixels, and n first data lines spaced apart from each other, disposed between the 1-1st pixel and the 1-2nd pixel in a plan view, extending in a second direction crossing the first direction, and electrically connected to the 1-1st pixel and the 1-2nd pixel.

Abstract: A tiling display device includes a first display panel and a second display panel that is spaced apart from the first display panel by a horizontal tiling interval. The first display panel includes first to (n)-th pixel columns, and the second display panel includes first to (m)-th pixel columns. A first distance between the (n)-th pixel column of the first display panel and the first pixel column of the second display panel is less than a second distance between a (n?1)-th pixel column of the first display panel and the (n)-th pixel column of the first display panel.

Abstract: A display device according to an embodiment may include a first sub-display panel and a second sub-display panel adjacent to the first sub-display panel in a first direction. The first sub-display panel may include a first pixel adjacent to the second sub-display panel and a first ground line disposed between the first pixel and the second sub-display panel and extending in a second direction crossing the first direction. The second sub-display panel may include a second pixel adjacent to the first sub-display panel and a second ground line disposed between the second pixel and the first sub-display panel and extending in the second direction.

Abstract: Provided is a tiled display device including a first sub-display panel on which a plurality of unit pixels is formed, and a second sub-display panel on which a plurality of unit pixels is formed, and located adjacent to the first sub-display panel, wherein each of the unit pixels includes a display element for emitting colored light, and a plurality of sub-pixels having a pixel circuit for driving the display element, and wherein an arrangement order of sub-pixels in the unit pixels corresponding to a current row, and an arrangement order of the sub-pixels in the unit pixels corresponding to a previous row or a next row, are different from each other.

Abstract: A display apparatus includes a display panel, a data driving circuit and a gate driving circuit. The display panel displays an image and includes a plurality of pixels. The data driving circuit applies a data voltage to a data line of the display panel. The gate driving circuit applies a gate output signal to a gate line of the display panel. The gate driving circuit is disposed between opening portions in a display area of the display panel. The gate driving circuit includes a normal stage column extending in a pixel column direction of the display panel and including a plurality of normal stages and a dummy stage column disposed adjacent to an end portion of the normal stage column in a pixel row direction and including a plurality of dummy stages.

Abstract: A display panel includes: a display substrate including a display area and a pad area spaced apart from a side of the display area in a first direction; and first to (n)th signal pads (where n is an integer of 2 or more) in the pad area on the display substrate, extending in the first direction, and spaced apart from each other in a second direction perpendicular to the first direction, wherein a (k)th signal pad among the first to (n)th signal pads (where k is an integer between 1 and n) is between the first signal pad and the (n)th signal pad, wherein a length of each of (k)th to (n)th signal pads among the first to (n)th signal pads along the first direction gradually increases, and wherein a width of each of the (k)th to (n)th signal pads along the second direction gradually decreases.

Abstract: A display panel includes a first sub-display panel, a second sub-display panel adjacent to the first sub-display panel in a first direction, and a connection member electrically connecting the first sub-display panel to the second sub-display panel. The first sub-display panel includes a first pixel, a second pixel between and adjacent to the first pixel and the second sub-display panel, a first low power voltage line for transferring a power voltage to the first pixel, and a first gate line electrically connected to the first pixel and the second pixel, the second pixel receives the power voltage from the first low power voltage line, the second sub-display panel includes a third pixel adjacent to the first sub-display panel, and the third pixel is electrically connected to the first gate line.