Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal, generated when the bandgap reference circuit starts up, to mirror a base current to generate a first current and a second current. The current generating circuit is arranged to output the first current when triggered by the triggered signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage. When the first current reduces to a predetermined level, the control circuit activates generation of the switch control signal to control the switch circuit.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal, generated when the bandgap reference circuit starts up, to mirror a base current to generate a first current and a second current. The current generating circuit is arranged to output the first current when triggered by the triggered signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage. When the first current reduces to a predetermined level, the control circuit activates generation of the switch control signal to control the switch circuit.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.

Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.

Abstract: A bandgap reference circuit includes: a current generating circuit, a start-up circuit, a switch circuit, and a control circuit. The current generating circuit is arranged to generate a reference current according to a control signal on a control node. The start-up circuit is coupled to the current generating circuit and arranged to generate a trigger signal and output the trigger signal as the control signal when the bandgap reference circuit starts up. The switch circuit is coupled to the current generating circuit and arranged to generate a bandgap voltage according to the reference current, and the bandgap voltage is outputted to a regulator coupled to the bandgap reference circuit. The control circuit is coupled to the control node and the switch circuit and arranged to generate a switch control signal according to the trigger signal, and the switch control signal controls a switch status of the switch circuit.

Abstract: A capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed. The first capacitance phase interpolation unit includes a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling, and the first capacitance phase interpolation unit receives a plurality of reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, wherein a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained via the first capacitance phase interpolation unit and the second capacitance phase interpolation unit by performing phase interpolation on all the reference clock signals.

Abstract: A capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed. The first capacitance phase interpolation unit includes a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling, and the first capacitance phase interpolation unit receives a plurality of reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, wherein a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained via the first capacitance phase interpolation unit and the second capacitance phase interpolation unit by performing phase interpolation on all the reference clock signals.

Abstract: A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal.

Abstract: A radio frequency (RF) front-end circuit and an operating method thereof are provided. The proposed RF front-end circuit includes a first linear amplifier, a second linear amplifier, and a calibration unit. The first linear amplifier performs a high-frequency amplification on a RF signal to generate an amplified RF signal, and down-converts the amplified RF signal into an intermediate frequency (IF) signal. The second first linear amplifier performs a low-frequency amplification on the IF signal to generate an amplified IF signal. The calibration unit is coupled to the first and the second linear amplifiers, and receives a voltage gain fed back from the second linear amplifier. Then, the calibration unit performs an auto-calibration procedure according to the voltage gain fed back from the second linear amplifier to search for an input current value of the first linear amplifier, which correspondingly maximizes the voltage gain of the first amplifier.

Abstract: A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal.

Abstract: A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

Abstract: A radio frequency (RF) front-end circuit and an operating method thereof are provided. The proposed RF front-end circuit includes a first linear amplifier, a second linear amplifier, and a calibration unit. The first linear amplifier performs a high-frequency amplification on a RF signal to generate an amplified RF signal, and down-converts the amplified RF signal into an intermediate frequency (IF) signal. The second first linear amplifier performs a low-frequency amplification on the IF signal to generate an amplified IF signal. The calibration unit is coupled to the first and the second linear amplifiers, and receives a voltage gain fed back from the second linear amplifier. Then, the calibration unit performs an auto-calibration procedure according to the voltage gain fed back from the second linear amplifier to search for an input current value of the first linear amplifier, which correspondingly maximizes the voltage gain of the first amplifier.

Abstract: A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

Abstract: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.