Patents by Inventor Nai-Cheng Lu

Nai-Cheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190035598
    Abstract: A semiconductor device includes a tube-like structure comprising a plurality of dielectric layers and conductor layers that are disposed on top of one another; a conductor tip integrally formed with a cap conductor layer that is disposed on a top surface of the tube-like structure, wherein the conductor tip extends to a central hole of the tube-like structure; and at least one photodetector formed within a bottom portion of the tube-like structure.
    Type: Application
    Filed: February 21, 2018
    Publication date: January 31, 2019
    Inventors: Hsien-Yu CHANG, Nai-Cheng LU
  • Patent number: 9880220
    Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huang-Ting Hsiao, An-Tai Xu, Pei-Haw Tsao, Cheng-Hung Tsai, Tsui-Mei Chen, Nai-Cheng Lu
  • Publication number: 20160356846
    Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 8, 2016
    Inventors: HUANG-TING HSIAO, AN-TAI XU, PEI-HAW TSAO, CHENG-HUNG TSAI, TSUI-MEI CHEN, NAI-CHENG LU
  • Patent number: 9454684
    Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huang-Ting Hsiao, An-Tai Xu, Pei-Haw Tsao, Cheng-Hung Tsai, Tsui-Mei Chen, Nai-Cheng Lu
  • Publication number: 20150347793
    Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: HUANG-TING HSIAO, AN-TAI XU, PEI-HAW TSAO, CHENG-HUNG TSAI, TSUI-MEI CHEN, NAI-CHENG LU
  • Patent number: 6909300
    Abstract: A method for fabricating an electrical test apparatus electrical probe tip first provides a probe tip substrate having a topographic surface. A high density plasma chemical vapor deposition (HDP-CVD) deposited mandrel layer is then formed upon the topographic surface. It has a series of pointed tips formed over a series of topographic features within the topographic surface. Finally, a conductor probe tip layer is formed conformally upon the high density plasma chemical vapor deposition (HDP-CVD) deposited mandrel layer and replicating the series of pointed tips. Due to the series of pointed tips and the series of replicated pointed tips, a microelectronic fabrication when tested with the electrical test apparatus electrical probe tip is tested with enhanced accuracy.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: June 21, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Nai-Cheng Lu, Yu-Ting Liao, Fu-Sung Liu
  • Publication number: 20030210065
    Abstract: Within a method for fabricating an electrical test apparatus electrical probe tip, there first provided a probe tip substrate comprising a topographic surface. There is then formed upon the topographic surface a high density plasma chemical vapor deposition (HDP-CVD) deposited mandrel layer having formed therein a series of pointed tips formed over a series of topographic features within the topographic surface. Finally, there is formed conformally upon the high density plasma chemical vapor deposition (HDP-CVD) deposited mandrel layer and replicating the series of pointed tips a conductor probe tip layer. Due to the series of pointed tips and the series of replicated pointed tips, a microelectronic fabrication when tested with the electrical test apparatus electrical probe tip is tested with enhanced accuracy.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Cheng Lu, Yu-Ting Liao, Fu-Sung Liu
  • Patent number: 6344674
    Abstract: In this invention a micro vacuum tube is used to form a flash memory cell. The micro vacuum tube is position over a floating gate and is used to program, erase, read and deselect the flash memory cell. A first embodiment includes a source and drain with the floating gate to provide a means to produce bit line current to be read by the flash memory sense amplifiers. In a second embodiment the source and drain are eliminated and cathode gate current is used to indicate the state of the flash memory cell. In a third embodiment the floating gate is replace with a diffusion in the semiconductor substrate. The cathode tip is formed by filling a depression in a sacrificial material used to temporarily fill the volume that will be the vacuum chamber when the vacuum tube is completed. The tip can be a convex cusp producing a needle like point or an elongated convex cusp having an sharp line edge.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: February 5, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Nai-Cheng Lu
  • Publication number: 20010010649
    Abstract: In this invention a micro vacuum tube is used to form a flash memory cell. The micro vacuum tube is position over a floating gate and is used to program, erase, read and deselect the flash memory cell. A first embodiment includes a source and drain with the floating gate to provide a means to produce bit line current to be read by the flash memory sense amplifiers. In a second embodiment the source and drain are eliminated and cathode gate current is used to indicate the state of the flash memory cell. In a third embodiment the floating gate is replace with a diffusion in the semiconductor substrate. The cathode tip is formed by filling a depression in a sacrificial material used to temporarily fill the volume that will be the vacuum chamber when the vacuum tube is completed. The tip can be a convex cusp producing a needle like point or an elongated convex cusp having an sharp line edge.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 2, 2001
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventor: Nai-Cheng Lu
  • Patent number: 6212104
    Abstract: In this invention a micro vacuum tube is used to form a flash memory cell. The micro vacuum tube is position over a floating gate and is used to program, erase, read and deselect the flash memory cell. A first embodiment includes a source and drain with the floating gate to provide a means to produce bit line current to be read by the flash memory sense amplifiers. In a second embodiment the source and drain are eliminated and cathode gate current is used to indicate the state of the flash memory cell. In a third embodiment the floating gate is replace with a diffusion in the semiconductor substrate. The cathode tip is formed by filling a depression in a sacrificial material used to temporarily fill the volume that will be the vacuum chamber when the vacuum tube is completed. The tip can be a convex cusp producing a needle like point or an elongated convex cusp having an sharp line edge.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: April 3, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Nai-Cheng Lu
  • Patent number: 6194829
    Abstract: A micro vacuum tube includes a disk (7) having an axis and formed of successive planar layers of a first conductive layer (2), a first dielectric layer (3), a second conductive layer (4), and a second dielectric layer(5), a hole along the axis of the cylinder extends through the first dielectric layer (3), the second conductive layer (4), and the second dielectric layer (5), a cusp shaped microtip (62) centrally located over, and extending into, the hole is separated from and supported by, a pole (75) that rests on the second dielectric layer, and a cap (82) seals the microtip, the pole (75) and the hole in a permanent vacuum environment.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: February 27, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Nai-Cheng Lu
  • Patent number: 6083069
    Abstract: A micro vacuum tube is described. The process for manufacturing it begins with the deposition of two layers of polysilicon or metal, separated by dielectric layers, topping them with a layer of silicon nitride, and forming these into the shape of a disk. A hole is etched in the silicon nitride and then lined with a spacer, causing the width of the hole to decrease from top to bottom. When the hole is partially filled with a sacrificial layer the latter has a depression at its center which may be used as a mold for a microtip. To allow for easy removal of the sacrificial layer, pole holes are etched in it. These become support poles after the microtip material has been deposited over the sacrificial layer (which gets removed in its entirety). As an alternative to a microtip, a micro razor edge may be used for the cold emitter. A cap deposited over the structure while it is in vacuo serves to keep it under permanent vacuum.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: July 4, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Nai-Cheng Lu