Patents by Inventor Nai-Chia Chen
Nai-Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923199Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.Type: GrantFiled: June 21, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Patent number: 11495684Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.Type: GrantFiled: April 27, 2020Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
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Publication number: 20220319850Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
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Patent number: 11398380Abstract: A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.Type: GrantFiled: May 8, 2020Date of Patent: July 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Patent number: 10755972Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.Type: GrantFiled: March 20, 2017Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao
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Publication number: 20200266065Abstract: A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.Type: ApplicationFiled: May 8, 2020Publication date: August 20, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
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Publication number: 20200259017Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
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Patent number: 10658179Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.Type: GrantFiled: August 17, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Patent number: 10636908Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.Type: GrantFiled: November 30, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
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Publication number: 20200058502Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Patent number: 10553720Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.Type: GrantFiled: October 27, 2017Date of Patent: February 4, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Han Chu, Nai-Chia Chen, Jui-Ming Shih, Ping-Jung Huang, Tsung-Min Chuo, Bi-Ming Yen
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Patent number: 10354913Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.Type: GrantFiled: November 1, 2017Date of Patent: July 16, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
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Publication number: 20190097052Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.Type: ApplicationFiled: November 30, 2018Publication date: March 28, 2019Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
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Publication number: 20180350664Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.Type: ApplicationFiled: November 1, 2017Publication date: December 6, 2018Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
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Publication number: 20180151421Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.Type: ApplicationFiled: March 20, 2017Publication date: May 31, 2018Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao
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Publication number: 20180151735Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.Type: ApplicationFiled: October 27, 2017Publication date: May 31, 2018Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Han Chu, Nai-Chia Chen, Jui-Ming Shih, Ping-Jung Huang, Tsung-Min Chuo, Bi-Ming Yen