Patents by Inventor Nai-Chih Chang

Nai-Chih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939431
    Abstract: The present invention relates to a composition comprising an amino acid-modified polymer, a carboxypolysaccharide, and may further include a metal ion for anti-adhesion and vector application. More specifically, the invention relates to a thermosensitive composition having enhanced mechanical and improved water-erosion resistant properties for efficiently preventing tissue adhesions and can serve as a vector with bio-compatible, bio-degradable/absorbable, and in-vivo sustainable properties.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
  • Patent number: 11939432
    Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
  • Patent number: 9864711
    Abstract: Examples are disclosed for automatic downstream to upstream mode switching at a universal serial bus (USB) physical (PHY) layer including activating a switching structure to switch a USB port operating in a downstream mode to an upstream mode based on an attempted attachment by another USB port also operating in a downstream mode. The examples may also include facilitating attachment of the switched USB port now operating in the upstream mode to the other USB port operating in the downstream mode.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jennifer C. Wang, Alejandro Lenero Beracoechea, Nai-Chih Chang, Steven B. McGowan
  • Patent number: 8626979
    Abstract: A signal transmission system includes a controller interface, a protocol engine to convert data based on at least one protocol, and a common protocol interface coupled between the controller interface and the protocol engine. The controller interface includes or is coupled to a common dispatcher, and the data is to be transmitted between the controller interface and protocol engine through the common protocol interface and common dispatcher. The same protocol engine may convert data into different protocols, with all of the converted data be transmitted to or received from the controller interface through the common dispatcher and common protocol interface.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventors: Jennifer C. Wang, Nai-Chih Chang, Beracoecha Alejandro Lenero, Yew-Kee E. Wong
  • Publication number: 20130275640
    Abstract: Examples are disclosed for automatic downstream to upstream mode switching at a universal serial bus (USB) physical (PHY) layer including activating a switching structure to switch a USB port operating in a downstream mode to an upstream mode based on an attempted attachment by another USB port also operating in a downstream mode. The examples may also include facilitating attachment of the switched USB port now operating in the upstream mode to the other USB port operating in the downstream mode.
    Type: Application
    Filed: December 16, 2011
    Publication date: October 17, 2013
    Inventors: Jennifer C. Wang, Alejandro Lenero Beracoechea, Nai-Chih Chang, Steven B. McGowan
  • Patent number: 8539131
    Abstract: Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Jennifer C. Wang, Alejandro Lenero Beracoechea
  • Publication number: 20120166692
    Abstract: A signal transmission system includes a controller interface, a protocol engine to convert data based on at least one protocol, and a common protocol interface coupled between the controller interface and the protocol engine. The controller interface includes or is coupled to a common dispatcher, and the data is to be transmitted between the controller interface and protocol engine through the common protocol interface and common dispatcher. The same protocol engine may convert data into different protocols, with all of the converted data be transmitted to or received from the controller interface through the common dispatcher and common protocol interface.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Jennifer C. WANG, Nai-Chih Chang, Beracoecha Alejandro Lenero, Yew-Kee E. Wong
  • Publication number: 20120079145
    Abstract: Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Nai-Chih Chang, Jennifer C. Wang, Alejandro Lenero Beracoechea
  • Patent number: 8112507
    Abstract: According to one embodiment, a device is disclosed. The device includes a first protocol engine (PE) to process tasks to be forwarded to a first remote node, a remote node search unit (RNSU) having a three-dimensional (3-D) task list corresponding to tasks to be forwarded to the two or more sub-nodes, and a connection pointer to maintain a connection between the first PE and the first remote node.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Pak-lung Seto
  • Patent number: 7984208
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Tracey Gustafson, Pak-lung Seto, Gary Y. Tsao, Nai-Chih Chang, Victor Lau
  • Patent number: 7664889
    Abstract: A storage device is disclosed. The storage device includes a storage controller. The storage controller includes a direct memory access (DMA) Descriptor Manager (DM) to generate DMA descriptors by monitoring user data and a data integrity field (DIF) transferred between a host memory and a local memory based upon a function being performed.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Kiran Vemula, Pak-Iung Seto, Victor Lau, William Halleck, Nai-Chih Chang
  • Patent number: 7620751
    Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Victor Lau, Pak-lung Seto
  • Publication number: 20090125908
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 14, 2009
    Inventors: Tracey L. Gustafson, Pak-lung Seto, Gary Y. Tsao, Nai-Chih Chang, Victor Lau
  • Patent number: 7516257
    Abstract: According to one embodiment, a system is disclosed. The system includes an initiator device to transmit input/output (I/O) write data and a target device, coupled to the initiator device, to receive the write data from the initiator device as a first segment of data and a second segment of data. The target device re-transmits a transfer ready frame to force the initiator device to retransmit the second segment in response to detecting an uncorrectable error in the second segment.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Victor Lau, Pak-lung Seto, Nai-Chih Chang
  • Patent number: 7451255
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Tracey Gustafson, Pak-lung Seto, Gary Y. Tsao, Nai-Chih Chang, Victor Lau
  • Patent number: 7450588
    Abstract: According to one embodiment, a system is disclosed. The system includes an input/output (IO) frame manager (IOFM) to route received IO frames to one or more IO lists and one or more IO frame order managers (IOFOMs) to reorder frames received for each IO list according to a relative order.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Pak-lung Seto
  • Patent number: 7418615
    Abstract: According to one embodiment, a system is disclosed. The system includes a central timeout manager (CTM) to receive timeout events from two or more clients and a search unit to search for a location in a list of timeout events to place a new received timeout event.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Pak-Iung Seto, Victor Lau
  • Patent number: 7415549
    Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Kiran Vemula, Victor Lau, Pak-lung Seto, Nai-Chih Chang, William Halleck, Suresh Chemudupati, Ankit Parikh, Gary Y. Tsao
  • Publication number: 20080126608
    Abstract: According to one embodiment, a system is disclosed. The system includes an input/output (IO) frame manager (IOFM) to route received IO frames to one or more IO lists and one or more IO frame order managers (IOFOMs) to reorder frames received for each IO list according to a relative order.
    Type: Application
    Filed: August 24, 2006
    Publication date: May 29, 2008
    Inventors: Nai-Chih Chang, Pak-lung Seto
  • Patent number: 7366817
    Abstract: Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Nai-chih Chang, Pak-lung Seto, Victor Lau