Patents by Inventor Nai-Hao Kao

Nai-Hao Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200328142
    Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.
    Type: Application
    Filed: August 12, 2019
    Publication date: October 15, 2020
    Inventors: Don-Son Jiang, Nai-Hao Kao, Chih-Sheng Lin, Szu-Hsien Chen, Chih-Yuan Shih, Chia-Cheng Chen, Yu-Cheng Pai, Hsuan-Hao Mi
  • Patent number: 8207620
    Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 26, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yuan-Lin Tzeng, Nai-Hao Kao, Jeng-Yuan Lai, Yu-Po Wang, Cheng-Hsu Hsiao
  • Publication number: 20080017983
    Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 24, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Yuan-Lin Tzeng, Nai-Hao Kao, Jeng-Yuan Lai, Yu-Po Wang, Cheng-Hsu Hsiao
  • Patent number: 6819565
    Abstract: A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: November 16, 2004
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Nai-Hao Kao, Yu-Po Wang, Wen-Jung Chiang
  • Publication number: 20040070948
    Abstract: A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.
    Type: Application
    Filed: January 14, 2003
    Publication date: April 15, 2004
    Applicant: Siliconware Precision Industries, Ltd. Taiwan
    Inventors: Nai-Hao Kao, Yu-Po Wang, Wen-Jung Chiang