Patents by Inventor Nai-Hao YANG

Nai-Hao YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230317459
    Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Chun-Hsu Yang, Huei-Wen Hsieh, Nai-Hao Yang, Yu-Cheng Hsiao, Chun-Sheng Chen, Che-Wei Tien, Kuan-Chia Chen
  • Patent number: 11694899
    Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
  • Publication number: 20220384255
    Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
  • Publication number: 20210217622
    Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.
    Type: Application
    Filed: June 9, 2020
    Publication date: July 15, 2021
    Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
  • Patent number: 11018055
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Publication number: 20200144112
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 7, 2020
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Patent number: 10522399
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Patent number: 10438846
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Publication number: 20190164827
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Application
    Filed: November 30, 2018
    Publication date: May 30, 2019
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Publication number: 20190164825
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao YANG, Hung-Wen SU, Kuan-Chia CHEN