Abstract: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract: A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.