Patents by Inventor Nai-Wen Cheng
Nai-Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230341887Abstract: To increase an overall access speed and a performance of a bus system, in the present disclosure, a master device is designed to use a clock signal with different clock frequencies to address slave devices and read/write data from/to the slave devices. In an address phase, a first operating frequency which the master device can successfully address the slave devices is used as a clock frequency of the clock signal for addressing. In a read/write phase, a minimum one (i.e., a second operating frequency) of multiple working frequencies of the slave devices is used as the clock frequency of the clock signal for reading/writing, wherein the master device is connected to the slave devices via a bus. The working frequency of the slave device means a maximum clock frequency supported by the slave device.Type: ApplicationFiled: January 10, 2023Publication date: October 26, 2023Inventor: NAI-WEN CHENG
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Patent number: 11646247Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.Type: GrantFiled: November 30, 2020Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
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Patent number: 11552027Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.Type: GrantFiled: June 7, 2021Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
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Patent number: 11321091Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.Type: GrantFiled: May 11, 2020Date of Patent: May 3, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Nai-Wen Cheng, Tzu-Lan Shen
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Publication number: 20210296258Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
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Patent number: 11037885Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.Type: GrantFiled: August 12, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
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Publication number: 20210124584Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.Type: ApplicationFiled: May 11, 2020Publication date: April 29, 2021Inventors: Nai-Wen CHENG, Tzu-Lan SHEN
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Publication number: 20210082787Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
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Publication number: 20210050303Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.Type: ApplicationFiled: August 12, 2019Publication date: February 18, 2021Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
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Patent number: 10867891Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.Type: GrantFiled: April 23, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
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Publication number: 20200135617Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.Type: ApplicationFiled: April 23, 2019Publication date: April 30, 2020Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
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Patent number: 10074680Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: GrantFiled: March 4, 2016Date of Patent: September 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Publication number: 20160190190Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Patent number: 9299734Abstract: A method of preparing an active pixel cell on a substrate includes exerting a first stress on the substrate by forming a shallow trench isolation (STI) structure in the substrate. The method further includes testing the stressed substrate using Raman spectroscopy at a plurality of locations on the stress substrate. The method further includes depositing a stress layer having a second stress on the substrate. The stress layer covers devices of the active pixel cell that are on the substrate and the devices include a photodiode next to the STI and a transistor, and the deposition of the stress layer results in the second stress being exerted on the substrate, the second stress countering the first stress.Type: GrantFiled: September 4, 2013Date of Patent: March 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Shang Hsiao, Nai-Wen Cheng, Chung-Te Lin, Chien-Hsien Tseng, Shou-Gwo Wuu
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Patent number: 9299740Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: GrantFiled: October 12, 2012Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Patent number: 8778717Abstract: A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.Type: GrantFiled: March 17, 2010Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Shang Hsiao, Chung-Te Lin, Nai-Wen Cheng, Yin-Kai Liao, Wei Chuang Wu
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Publication number: 20140001523Abstract: A method of preparing an active pixel cell on a substrate includes exerting a first stress on the substrate by forming a shallow trench isolation (STI) structure in the substrate. The method further includes testing the stressed substrate using Raman spectroscopy at a plurality of locations on the stress substrate. The method further includes depositing a stress layer having a second stress on the substrate. The stress layer covers devices of the active pixel cell that are on the substrate and the devices include a photodiode next to the STI and a transistor, and the deposition of the stress layer results in the second stress being exerted on the substrate, the second stress countering the first stress.Type: ApplicationFiled: September 4, 2013Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Shang HSIAO, Nai-Wen CHENG, Chung-Te LIN, Chien-Hsien TSENG, Shou-Gwo WUU
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Publication number: 20130320469Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: ApplicationFiled: October 12, 2012Publication date: December 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Patent number: 8546860Abstract: This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.Type: GrantFiled: June 12, 2012Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Shang Hsiao, Nai-Wen Cheng, Chung-Te Lin, Chien-Hsien Tseng, Shou-Gwo Wuu
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Patent number: 8389377Abstract: The present disclosure provides methods and apparatus for sensor element isolation in a backside illuminated image sensor. In one embodiment, a method of fabricating a semiconductor device includes providing a sensor layer having a frontside surface and a backside surface, forming a plurality of frontside trenches in the frontside surface of the sensor layer, and implanting oxygen into the sensor layer through the plurality of frontside trenches. The method further includes annealing the implanted oxygen to form a plurality of first silicon oxide blocks in the sensor layer, wherein each first silicon oxide block is disposed substantially adjacent a respective frontside trench to form an isolation feature. A semiconductor device fabricated by such a method is also disclosed.Type: GrantFiled: April 2, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Shang Hsiao, Kun-Yu Tsai, Chien-Hsien Tseng, Shou-Gwo Wuu, Nai-Wen Cheng