Patents by Inventor Naiju K. Abdul
Naiju K. Abdul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10354046Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: GrantFiled: November 13, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Patent number: 10318683Abstract: A system and method to generate a clock domain-independent abstract of a component in an integrated circuit design. The method includes performing an initial analysis of the component using an initial clock value for each clock domain type, the clock domain types including a functional clock and a test clock, executing an abstractor to obtain a reduced order model of the initial analysis as a clock domain-dependent abstract, and obtaining original constraints associated with one or more circuit elements within the component from the clock domain-dependent abstract. Generating generalized constraints is based on clock domain-dependent constraints among the original constraints, and generating the clock domain-independent abstract is based on the generalized constraints. The method also includes obtaining a physical implementation based on one or more analyses using the clock domain-independent abstract.Type: GrantFiled: May 20, 2016Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Jack DiLullo, Kerim Kalafala, Jeremy J. Leitzen, Manish Verma
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Patent number: 10169503Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: GrantFiled: February 15, 2018Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Publication number: 20180173833Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Patent number: 9977850Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: GrantFiled: July 12, 2016Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Publication number: 20180068051Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: ApplicationFiled: November 13, 2017Publication date: March 8, 2018Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Patent number: 9910954Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: GrantFiled: May 26, 2016Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Publication number: 20180018421Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Publication number: 20170344693Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: ApplicationFiled: May 26, 2016Publication date: November 30, 2017Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Publication number: 20170337313Abstract: A system and method to generate a clock domain-independent abstract of a component in an integrated circuit design. The method includes performing an initial analysis of the component using an initial clock value for each clock domain type, the clock domain types including a functional clock and a test clock, executing an abstractor to obtain a reduced order model of the initial analysis as a clock domain-dependent abstract, and obtaining original constraints associated with one or more circuit elements within the component from the clock domain-dependent abstract. Generating generalized constraints is based on clock domain-dependent constraints among the original constraints, and generating the clock domain-independent abstract is based on the generalized constraints. The method also includes obtaining a physical implementation based on one or more analyses using the clock domain-independent abstract.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Inventors: Naiju K. Abdul, Adil Bhanji, Jack DiLullo, Kerim Kalafala, Jeremy J. Leitzen, Manish Verma