Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

Abstract: A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate (101) having a second conductivity type; a drift region (102) that has a first conductivity type and is disposed on the substrate (101), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (102), each layer of the doped structure comprising at least one doped bar (105) extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars (106) disposed in the drift region (102) so as to extend downward through the doped bar (105) of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars (106) and ions doped in the doped bar have opposite conductivity types.

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

Abstract: A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

Abstract: The present disclosure provides a lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method includes: providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate; forming a drain region in the drift region, forming a source region in the body region, and forming, on the body region, a gate structure extending to the drift region; implanting ions of a first type, so as to form, at a bottom of the drift region, first ion implantation regions extending along a direction from the gate structure to the drain region; forming, above the first ion implantation regions, a plurality of mutually spaced deep trench structures and fin structures between adjacent ones of the deep trench structures; and implanting ions of a second type in the deep trench structures to form second ion implantation regions.

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

Abstract: The disclosure relates to integrated circuit (IC) structures and fabrication techniques. Methods according to the disclosure can include: providing a precursor structure including: a first inter-metal dielectric (IMD); a barrier dielectric positioned on the first IMD; forming an insulator on the barrier dielectric of the precursor structure, wherein an upper surface of the insulator includes a first trench and a second trench laterally separated from the first trench; forming an alignment marker over the precursor structure by filling the first trench with a first refractory metal film; forming a first metal-insulator-metal (MIM) electrode by filling the second trench with the first refractory metal film; recessing the insulator without exposing an upper surface of the barrier dielectric; forming a MIM dielectric layer on the insulator; and forming a second MIM electrode on the MIM dielectric layer, such that the second MIM electrode overlies a portion of the first MIM electrode.