Patents by Inventor Naiqian Lu

Naiqian Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11924435
    Abstract: Techniques related to parallel partitioning and coding mode selection for improved video coding throughput are discussed. Such techniques include performing parallel partitioning and coding mode selection for a lower-right coding unit of a first largest coding unit and an upper-left coding unit of a second largest coding unit to the right of the first largest coding unit and, immediately subsequent thereto, performing parallel partitioning and coding mode selection for a lower-left coding unit and an upper-right coding unit of the second largest coding unit.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Srinivasan Embar Raghukrishnan, Jason Tanner, Naiqian Lu
  • Patent number: 11150943
    Abstract: Independent workloads may be grouped together into a single super workload. This super workload is dispatched to a single context hardware system that does not run an operating system. This effectively creates a multi-context system out of a single context hardware processor.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Changwon D. Rhee, Zhijun R. Lei, Ping Liu, Kin-Hang W. Cheung, Gomathi Ramamurthy, Naiqian Lu, Sang-Hee Lee, Wei Xiong, Richard Gui Xie, Saimanohara S. Alapati, Jay M. Patel
  • Publication number: 20200280722
    Abstract: Techniques related to parallel partitioning and coding mode selection for improved video coding throughput are discussed. Such techniques include performing parallel partitioning and coding mode selection for a lower-right coding unit of a first largest coding unit and an upper-left coding unit of a second largest coding unit to the right of the first largest coding unit and, immediately subsequent thereto, performing parallel partitioning and coding mode selection for a lower-left coding unit and an upper-right coding unit of the second largest coding unit.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Srinivasan Embar Raghukrishnan, Jason Tanner, Naiqian Lu
  • Publication number: 20180293097
    Abstract: In some embodiments, independent workloads may be grouped together into a single super workload. This super workload is dispatched to a single context hardware system that does not run an operating system. This effectively creates a multi-context system out of a single context hardware processor.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Changwon D. Rhee, Zhijun R. Lei, Ping Liu, Kin-Hang W. Cheung, Gomathi Ramamurthy, Naiqian Lu, Sang-Hee Lee, Wei Xiong, Richard Gui Xie, Saimanohara S. Alapati, Jay M. Patel
  • Patent number: 6563874
    Abstract: A video compression method of estimating a motion vector representative of a difference between a reference frame and a current frame is described. Typically, both the reference frame and the current frame include background and foreground data. In the method a block of the current frame is selected for analysis, and a determination is made whether the block selected is a foreground block or a background block. If the block is a foreground block, then it is compared with predetermined search points in the reference frame. On the other hand, if the block is a background block, it is compared with predetermined search points in only a portion of the reference frame.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: May 13, 2003
    Assignee: Hitachi America, Ltd.
    Inventor: Naiqian Lu
  • Publication number: 20020136302
    Abstract: A video compression technique is provided which reduces motion estimation computations. A digital signal processing system employs external memory. Detection speed is improved by loading a succession of refined search windows are loaded on-chip. By so doing, the search involves fewer accesses to external memory and so completes in a shorter amount of time.
    Type: Application
    Filed: March 21, 2001
    Publication date: September 26, 2002
    Inventor: Naiqian Lu