Patents by Inventor Naiqian Ren
Naiqian Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230421171Abstract: Techniques to deliver a precision low noise reference voltage to a precision analog-to-digital converter without the need of a reference buffer or digital correction. In an example, a technique can use an integrated resistor divider and external capacitor to derive a low noise precision reference voltage either from the power supply of the ADC, or from an integrated reference source.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Naiqian Ren, Roberto Sergio Matteo Maurino
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Patent number: 11251807Abstract: A wide bandwidth ADC circuit that combines a resistive-input continuous-time sigma-delta ADC circuit with a second ADC circuit having a switched capacitor input. The combination of these two ADC circuits can achieve an easy-to-drive, alias free, wide bandwidth ADC that has excellent DC precision.Type: GrantFiled: November 10, 2020Date of Patent: February 15, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Naiqian Ren, Roberto Sergio Matteo Maurino
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Patent number: 11206040Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.Type: GrantFiled: May 5, 2020Date of Patent: December 21, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Naiqian Ren, Mary McCarthy
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Publication number: 20210351784Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.Type: ApplicationFiled: May 5, 2020Publication date: November 11, 2021Inventors: Naiqian Ren, Mary McCarthy
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Patent number: 10979062Abstract: This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.Type: GrantFiled: April 24, 2020Date of Patent: April 13, 2021Assignee: Analog Devices International Unlimited CompanyInventors: John P. Healy, Michael Hennessy, Naiqian Ren, Patrick Martin McGuinness, Robert A. Bombara
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Publication number: 20200252074Abstract: This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.Type: ApplicationFiled: April 24, 2020Publication date: August 6, 2020Inventors: John P. Healy, Michael Hennessy, Naiqian Ren, Patrick Martin McGuinness, Robert A. Bombara
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Publication number: 20200204185Abstract: This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: John P. Healy, Michael Hennessy, Naiqian Ren, Patrick Martin McGuinness, Robert A. Bombara
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Patent number: 10680633Abstract: This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP, The SIP can be configured for various applications based on a variety of inputs and control mechanisms.Type: GrantFiled: December 21, 2018Date of Patent: June 9, 2020Assignee: Analog Devices International Unlimited CompnayInventors: John P. Healy, Michael Hennessy, Naiqian Ren, Patrick Martin McGuinness, Robert A. Bombara
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Patent number: 9893877Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.Type: GrantFiled: October 27, 2016Date of Patent: February 13, 2018Assignee: Analog Devices GlobalInventors: Mayur Gurunath Anvekar, Venkata Aruna Srikanth Nittala, Roberto Sergio Matteo Maurino, Naiqian Ren
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Publication number: 20170207907Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.Type: ApplicationFiled: October 27, 2016Publication date: July 20, 2017Inventors: Mayur Gurunath Anvekar, Venkata Aruna Srikanth Nittala, Roberto Sergio Matteo Maurino, Naiqian Ren
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Publication number: 20140253176Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: Analog Devices TechnologyInventors: Finbarr O'Leary, Michael Edward Bradley, Naiqian Ren, George R. Spalding, Nigel David Brooke
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Patent number: 8823419Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.Type: GrantFiled: March 11, 2013Date of Patent: September 2, 2014Assignee: Analog Devices TechnologyInventors: Finbarr O'Leary, Michael Edward Bradley, Naiqian Ren, George R. Spalding, Nigel David Brooke