Patents by Inventor Najeeb Ansari

Najeeb Ansari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190046
    Abstract: Various example embodiments for supporting power optimizations for electronic circuits are presented. Various example embodiments for supporting power optimizations for electronic circuits may be configured to support power optimizations for a block of an electronic circuit. Various example embodiments for supporting power optimizations for a block of an electronic circuit may be configured to support a reduction in power consumption by a clock distribution tree of the block of the electronic circuit. Various example embodiments for supporting a reduction in power consumption by a clock distribution tree of a block of an electronic circuit may be configured to reduce power consumption by the clock distribution tree of the block of the electronic circuit by supporting root clock throttling for the block of the electronic circuit, based on a workload on the block of the electronic circuit, to reduce power consumption by the clock distribution tree of the block of the electronic circuit.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Inventors: Brian Alleyne, Hengwei Hsu, Najeeb Ansari
  • Patent number: 9128769
    Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 8, 2015
    Assignee: Cavium, Inc.
    Inventors: Jeffrey Schroeder, Jeff Pangborn, Najeeb Ansari, Bryan Chin, Leo Chen, Ahmed Shahid, Paul Scrobohaci, Chee Hu, Michael Carns, Wu Ye, Brian Hunter
  • Publication number: 20130097598
    Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: Cavium, Inc.
    Inventors: Jeffrey Schroeder, Jeff Pangborn, Najeeb Ansari, Bryan Chin, Leo Chen, Ahmed Shahid, Paul Scrobohaci, Chee Hu, Michael Carns, Wu Ye, Brian Hunter