Patents by Inventor Naji Chafic Naufel

Naji Chafic Naufel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic circuit having phased logic busses for reducing electromagnetic interference
    Patent number: 5802317
    Abstract: An electronic circuit (100) for reducing electromagnetic interference includes a plurality of circuit elements (130, 140, 150) to which a set of bussed logic signals (343) generated by a set of first circuits (342) is distributed by a logic clock (120). The electronic circuit (100) further includes a plurality of cascaded busses (355, 135, 335) including a last cascaded bus (335) having a last enablement phase. Each of the plurality of cascaded busses (355, 135, 335) couples a set of amplified logic signals (355, 135, 335) from one of the plurality of circuit elements (358, 359, 336) to another one of the plurality of circuit elements (359, 336, 322). The set of amplified logic signals (355, 135, 335) of each of the plurality of cascaded busses is enabled during an enable period (351, 352, 330) which lasts beyond an end of the last enablement phase.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: September 1, 1998
    Assignee: Motorola, Inc.
    Inventors: Carl Donald Wiseman, Naji Chafic Naufel, Sang Quan, Yong Hyon Kim