Abstract: A system (10) for testing one or more circuit boards (12.sub.1 -12.sub.n), each containing at least one chain of Boundary-Scan cells (14.sub.1 -14.sub.p), includes a system test and diagnosis host (16) for managing overall testing of the system formed by the circuit boards. A Boundary-Scan Virtual Machine (BVM) (17) is operative to receive an initiate test command from the system test and diagnosis host independent of the number and nature of the boards to be tested. In response to the test command, the BVM (17) causes each circuit board to execute a test program (23) specific thereto to determine the errors, if any, in the board. The errors from each board are passed back to the BVM (17) which, in turn, interprets the errors to yield test information, indicative of the operation of the boards, which is then passed back to the system test and diagnosis host (16).

Abstract: Both the input/output connections (16) of a circuit board (10) and the boundary scan devices (12.sub.1 -12.sub.n) thereon can be tested simultaneously by boundary scan techniques using a Serial Test Extension Module (STEM) (28) which mates with the circuit board. The STEM (28) contains at least one boundary scan register (36) which makes an electrical connection with a separate circuit board input/output connection (16) when the STEM mates with the board. The boundary scan registers (36) within the STEM (28) are serially connected in a chain, that is, connected in series with a chain of serially connected boundary scan registers (20) within the boundary scan devices (12.sub.1 -12.sub.n). By launching a known bit stream into the chain of boundary scan registers (20) and (36) and thereafter shifting out the bits and comparing them to a reference bit stream, representing a defect-free condition, faults in the input/output connections (16) and/or in the devices (12.sub.1 -12.sub.n) can be detected.

Abstract: A scheme is provided for efficient transfer of N separate L-bit segments of data (where N and L are integers) to or from an L-bit register (14) in a device under test (10) serially coupled with at least one other register in a device (10') in a scan chain. To carry out such data transfer, a stream of N L-bit segments of interest is first concatenated to, and ahead of, a packet of L.sub.1 filler bits, where L.sub.1 is the cumulative number of register cells in the chain of devices (10') upstream of the L-bit register (14) in the device under test (10). The stream of L.sub.1 +NL bits is applied to the chain by shifting the first L.sub.1 bits of the block of NL bits through the chain to flush the previous data stored in the registers upstream of the L-bit register in the device under test (10). The remaining bits in the stream of L.sub.1 +NL bits are then shifted through the chain of devices (10 and 10' ) until the L.sub.

Abstract: A method is disclosed for generating a control signal (TMS) which may be used to control the test activity of boundary scan system (10). The method is initiated by loading a multi-bit control macro (STI, DTI or DSTI) into a register (38) whose output is coupled back to its input. After loading of the macro, its identity is ascertained by a macro controller (42) which serves to decode a multi-bit signal (IT) whose state is indicative of the macro type. The macro controller (42) actuates the register to shift out the bits of the control macro in a sequence dependent on the macro's identity in order to generate the appropriate control signal. As each bit is shifted out, it is shifted back into the register so as to allow the same sequence of bits to be repeatedly shifted out.

Abstract: A test system (10) is associated with a chain of circuits (12) on a circuit board (13) for testing the interconnections (11) linking the circuits in the chain as well as for testing the interconnections linking them to those on other boards. The test system includes a controller (22) for generating a test signal and for capturing a response signal generated by the associated chain of circuits in response to the test signal. The controller (22) also generates a flow control signal which controls a network (24) that routes the test signals from the controller, or from a first other test system, to the associated chain of circuits (12). In accordance with the flow control signal, the network (24) also serves to route the response signal from the associated chain of circuits (12) to the controller (22) or to a second other test system.

Abstract: A set of test vectors for input to a circuit (10) to test the integrity of each of its n interconnections (nets) 16 is generated by first ordering the nets. Thereafter, the vectors are generated by assigning the bits of each vector associated with a given net a one or zero such that the vector has a minimum weight, as compared to the vectors assigned to successive nets. Alternatively, the test vectors can be generated by assigning the bits of selected groups of vectors a one or zero such that the groups of vectors each have minimum potential weight and the vectors in the group are independent of each other. The successive groups of vectors are then concatenated to yield the test vector set.

Abstract: The RAM is partitioned into modules, each of which appear as the leaf node of a binary interconnect network. This network carries the address/data/control bus which permits the nodes to communicate between themselves and with the outside world. The address, data and control signals are applied to the root node. The most significant address bit is decoded, generating either a left subtree or a right subtree select. The other signals would be buffered and propogated down the tree. The solution process occurs at each level within the bus until finally a single leaf node would be selected. Within the node, then, the internal timing and control unit would access the data requested, sending it up the tree or writing the value on the data bus, into the addressed location.