Abstract: The present invention relates to a semiconductor memory device. When a device exits from power mode, after a time until an instruction/address receive control signal substantially turns on or off an address and instruction input buffer unit and a time until the address and instruction buffer unit is turned on to synchronize an external command signal to an internal clock signal are compensated for, an internal clock-generating control signal for controlling generation of the internal clock signal is sensed at a high phase of a buffered clock signal and is generated at a low phase of the buffered clock signal. Further, when a device enters power mode, an internal clock-generating control signal for controlling generation of an internal clock signal is sensed at a high phase of a buffered clock signal and is then generated at a low phase of the buffered clock signal.

Abstract: Disclosed are a DDR group (DDR I, DDR II, DDR III, . . . ) data output control device for controlling a time point of data output by using a DLL circuit and a method thereof. The data output control device includes a latch part for storing data read out from a memory cell array through a read operation, a control part for controlling an operation of the latch part, and an initialization signal generating part for generating an initialization signal for resetting an operation of the control part, wherein the initialization signal is synchronized with a clock signal generated from a DLL circuit in the memory device.

Abstract: The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.