Patents by Inventor Naka Onoda

Naka Onoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100103392
    Abstract: The immersion exposure device cleaning method according to the invention includes: placing a dummy wafer onto a stage of the immersion exposure device; and moving the stage while maintaining an immersion solution between the dummy wafer and a projector lens. The dummy wafer includes a substrate and an adsorption area that is formed on the substrate and has higher adsorption power for particles suspended in the supplied immersion solution than the substrate has for the particles.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 29, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshinori Matsui, Naka Onoda
  • Patent number: 6198109
    Abstract: There is provided an apparatus used for forming a pattern on a substrate by photolithography with electron beams, the apparatus including (a) an aperture formed with at least one opening through which electron beams are to pass, and (b) a holder for fixedly supporting the aperture therewith by means an adhesive, at least one of surfaces of the aperture and the holder at which the aperture is adhesively fixed to the holder, being formed with at least one groove for excessive portion of the adhesive to flow in. When an aperture is fixed onto a holder with an adhesive, an adhesive may be excessively applied on a surface of the aperture or holder. However, in accordance with the above-mentioned apparatus, since excessive adhesive is pooled in the groove, it is possible to avoid the excessive adhesive from being forced out to the opening of the aperture, and thus, it is possible to avoid forming an incorrect pattern on a photoresist film.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: March 6, 2001
    Assignee: NEC Corporation
    Inventor: Naka Onoda
  • Patent number: 6103434
    Abstract: An electron beam direct drawing method has the steps of: converting drawing data for the electron beam direct drawing of a semiconductor device pattern on a chip into a predetermined size and shape; dividing the converted drawing data into multiple fields which are electron beam deflection regions; drawing the drawing data corresponding to each of the divided multiple fields on the chip by step and repeat method; wherein the converted drawing data dividing step is conducted such that the drawing data is divided into the multiple fields on the basis of the chip.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: August 15, 2000
    Assignee: NEC Corporation
    Inventor: Naka Onoda
  • Patent number: 6040583
    Abstract: An electron beam exposure system has a continuous stage drive for driving a stage at a constant speed. Area of a semiconductor chip is divided into an array of unit meshes to calculate pattern density in each mesh. A group of meshes having an equal density level is combined as a sub-strip region having dimensions equal to or lower than the maximum width determined based on the ability of the electron beam exposure system.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: March 21, 2000
    Assignee: NEC Corporation
    Inventor: Naka Onoda
  • Patent number: 5949079
    Abstract: A method and an apparatus for electron beam exposure convenient to be applied to the hybrid exposure of a pattern with ultra-fine design rules, a method of electron beam exposure comprises: a primary field dividing step (S2) for dividing a second pattern to be drawn into a plurality of fields having a size whereon an electron beam can be radiated with negligible biasing distortion; a primary fitting step for performing a fitting process (S3) for each of the plurality of fields, wherein cubic compensation equations are adjusted to fit compensation values with the optical distortion, and a fitting error after compensation being calculated; a primary field dividing step for performing a field dividing process (S5) for each of the plurality of fields whereof the fitting error is larger than a predetermined allowable range, wherein a concerning field is divided into a pair of sub fields and the fitting process is performed for each of the sub fields; and a sub field dividing step for repeating the field dividing p
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: September 7, 1999
    Assignee: NEC Corporation
    Inventor: Naka Onoda
  • Patent number: 5908733
    Abstract: To provide a method of and an apparatus for electron beam exposure convenient to be applied to the hybrid exposure of a pattern with ultra-fine design rules, a method of electron beam exposure according to an embodiment of the invention comprises: a primary field dividing step (S2) for dividing a second pattern to be drawn into a plurality of fields having a size whereon an electron beam can be radiated with negligible biasing distortion; a primary fitting step for performing a fitting process (S3) for each of the plurality of fields, wherein cubic compensation equations are adjusted to fit compensation values with the optical distortion, and a fitting error after compensation being calculated; a primary field dividing step for performing a field dividing process (S5) for each of the plurality of fields whereof the fitting error is larger than a predetermined allowable range, wherein a concerning field is divided into a pair of sub fields and the fitting process is performed for each of the sub fields; and a
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: June 1, 1999
    Assignee: NEC Corporation
    Inventor: Naka Onoda