Abstract: The present invention provides a storage system 1 comprising a host interface for receiving I/O requests from a host via a SAN, and a management interface for receiving network packets from a management terminal or other devices within a management network. The storage system analyzes the characteristics of I/O requests from the host, and changes a filter level based on the characteristics of the I/O requests. Further, the storage system executes control to increase the number of types of network packets to be abandoned out of the network packets arriving at the management interface when the filter level is high, and to reduce the number of types of network packets to be abandoned when the filter level is low, so as to prevent the processing of network packets arriving at the management interface from affecting the I/O performance of the host.

Abstract: The present invention enables program codes to be shared among processors 211. To prevent the debug operation of one processor 211 from affecting the debug operation of the other processors 211, when detecting a breakpoint during execution of a program code, a debugger 410 or a debugger stub 520 controls the execution of the program code while exchanging breakpoint information 800 with the other debuggers 410 or the other debugger stubs 520. Furthermore, a circuit 170 is created which prevents the program code being carelessly rewritten due to thermal runaway, a bug, and the like of a processor 211, and the protection setting by the protection logic 71 in the circuit 170 is released only in case the processor 211 accesses each of a plurality of registers from 65 to 67 in specified order.

Abstract: The present invention enables program codes to be shared among processors 211. To prevent the debug operation of one processor 211 from affecting the debug operation of the other processors 211, when detecting a breakpoint during execution of a program code, a debugger 410 or a debugger stub 520 controls the execution of the program code while exchanging breakpoint information 800 with the other debuggers 410 or the other debugger stubs 520. Furthermore, a circuit 170 is created which prevents the program code being carelessly rewritten due to thermal runaway, a bug, and the like of a processor 211, and the protection setting by the protection logic 71 in the circuit 170 is released only in case the processor 211 accesses each of a plurality of registers from 65 to 67 in specified order.

Abstract: Even if each processor core uses the same logical address, a processing-target program corresponding to each processor core can be selected. A logical address of multiple address mapping tables is set to a same logical address in correspondence with an embedded OS program or a RAID management program, and a physical address is set to a different physical address in correspondence with the actual storage destination of an embedded OS program or a RAID management program. Each processor core, on start-up, uses a self address mapping table to execute address mapping processing with each processor core based on the same logical address, selects an embedded OS program or a RAID management program according to the physical address obtained in the address mapping processing, and executes processing according to the selected program.

Abstract: Even if each processor core uses the same logical address, a processing-target program corresponding to each processor core can be selected. A logical address of multiple address mapping tables is set to a same logical address in correspondence with an embedded OS program or a RAID management program, and a physical address is set to a different physical address in correspondence with the actual storage destination of an embedded OS program or a RAID management program. Each processor core, on start-up, uses a self address mapping table to execute address mapping processing with each processor core based on the same logical address, selects an embedded OS program or a RAID management program according to the physical address obtained in the address mapping processing, and executes processing according to the selected program.

Abstract: A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.

Abstract: A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.