Patents by Inventor Nakae Nakamura
Nakae Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230068975Abstract: An imaging apparatus for an endoscope includes: a lens; an image sensor configured to capture an image via the lens; a light blocking portion provided covering the lens and the image sensor; a light source provided near the light blocking portion; and a light guide portion provided covering the light blocking portion and the light source and configured to guide light from the light source. The light blocking portion is provided so as to prevent the light from the light source from being incident on the lens and the image sensor. An end face of the lens is arranged at a position further recessed than at least an end face of the light blocking portion.Type: ApplicationFiled: August 12, 2022Publication date: March 2, 2023Inventors: NAKAE NAKAMURA, Nobuaki ASAYAMA, Tadahiko SATO, Yan QIAN
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Patent number: 9632609Abstract: The efficiency of a product cycle is considerably enhanced by avoiding loss from designing to production including member loss matching various sizes of touch sensor panels. Unit sensor sheets having a square outer shape on which a multiple number of sense lines 21 as a multiple number of conductive wirings are arranged in parallel, are disposed in 3 row, 3 column. Each end of each of the multiple number of sense lines 21 as a multiple number of conductive wirings is sequentially matched one-to-one between unit sensor sheets, for example, between the sensor sheets 2A and 2B, or the sensor sheets 2B and 2C, and electrically connected with each other, and thereby the respective multiple number of sense lines 21 as a multiple number of conductive wirings are connected in a longitudinal direction thereof and are integrated, in the 3 row, 3 column of the unit sensor sheets 2A-2I.Type: GrantFiled: April 7, 2014Date of Patent: April 25, 2017Assignee: Sharp Kabushiki KaishaInventors: Hiroaki Tsukamoto, Nakae Nakamura, Satoru Kudose, Nobuaki Asayama
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Patent number: 9489908Abstract: In order to realize display control of a display panel in which gate signals and source signals are supplied to the display panel via only one side of the display panel, a display device (1) includes a driving module (12) including: input terminals via which input signals from an input signal generating section (13) are supplied; output terminals via which gate signals and source signals are outputted; a gate driving circuit for generating the gate signals; and a source driving circuit for generating the source signals, and a display panel (11) in which control terminals are provided on only one side of the display panel (11).Type: GrantFiled: November 7, 2013Date of Patent: November 8, 2016Assignee: Sharp Kabushiki KaishaInventors: Yoshinari Marushima, Nakae Nakamura, Nobuaki Asayama
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Publication number: 20160098111Abstract: The efficiency of a product cycle is considerably enhanced by avoiding loss from designing to production including member loss matching various sizes of touch sensor panels. Unit sensor sheets having a square outer shape on which a multiple number of sense lines 21 as a multiple number of conductive wirings are arranged in parallel, are disposed in 3 row, 3 column. Each end of each of the multiple number of sense lines 21 as a multiple number of conductive wirings is sequentially matched one-to-one between unit sensor sheets, for example, between the sensor sheets 2A and 2B, or the sensor sheets 2B and 2C, and electrically connected with each other, and thereby the respective multiple number of sense lines 21 as a multiple number of conductive wirings are connected in a longitudinal direction thereof and are integrated, in the 3 row, 3 column of the unit sensor sheets 2A-2I.Type: ApplicationFiled: April 7, 2014Publication date: April 7, 2016Applicant: Sharp Kabushiki KaishaInventors: Hiroaki TSUKAMOTO, Nakae NAKAMURA, Satoru KUDOSE, Nobuaki ASAYAMA
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Publication number: 20160085346Abstract: In a touch panel module, speed up of reaction speed for an input operation, lower current consumption, and suppression of generation of heat in a sensor electrode are enhanced by attaining lower resistance of the sensor electrode.Type: ApplicationFiled: April 7, 2014Publication date: March 24, 2016Applicant: Sharp Kabushiki KaishaInventors: Hiroaki TSUKAMOTO, Nakae NAKAMURA, Nobuaki ASAYAMA
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Publication number: 20150302815Abstract: In order to realize display control of a display panel in which gate signals and source signals are supplied to the display panel via only one side of the display panel, a display device (1) includes a driving module (12) including: input terminals via which input signals from an input signal generating section (13) are supplied; output terminals via which gate signals and source signals are outputted; a gate driving circuit for generating the gate signals; and a source driving circuit for generating the source signals, and a display panel (11) in which control terminals are provided on only one side of the display panel (11).Type: ApplicationFiled: November 7, 2013Publication date: October 22, 2015Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshinari MARUSHIMA, Nakae NAKAMURA, Nobuaki ASAYAMA
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Connection structure for connecting semiconductor element and wiring board, and semiconductor device
Patent number: 7420282Abstract: In a connection structure of the present invention, the wiring board including a solder resist covering part which covers the wiring pattern with solder resist, the solder resist covering part having a solder resist opening or solder resist openings which expose(s) the wiring board connection terminals therethrough, and the solder resist opening or the solder resist openings surrounding at least one part of the solder resist covering part. Therefore, the wiring patterns are not unnecessarily exposed. That is, without disadvantageous contact between each wiring pattern and the semiconductor element, the semiconductor element can be mounted on the wiring board, and thus, the semiconductor device is reliable.Type: GrantFiled: October 17, 2005Date of Patent: September 2, 2008Assignee: Sharp Kabushiki KaishaInventors: Tomohiko Iwane, Nakae Nakamura -
Connection structure for connecting semiconductor element and wiring board, and semiconductor device
Publication number: 20060081999Abstract: In a connection structure of the present invention, the wiring board including a solder resist covering part which covers the wiring pattern with solder resist, the solder resist covering part having a solder resist opening or solder resist openings which expose(s) the wiring board connection terminals therethrough, and the solder resist opening or the solder resist openings surrounding at least one part of the solder resist covering part. Therefore, the wiring patterns are not unnecessarily exposed. That is, without disadvantageous contact between each wiring pattern and the semiconductor element, the semiconductor element can be mounted on the wiring board, and thus, the semiconductor device is reliable.Type: ApplicationFiled: October 17, 2005Publication date: April 20, 2006Inventors: Tomohiko Iwane, Nakae Nakamura -
Patent number: 6864562Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.Type: GrantFiled: June 21, 2000Date of Patent: March 8, 2005Assignee: Sharp Kabushiki KaishaInventors: Kenji Toyosawa, Atsushi Ono, Yasunori Chikawa, Nobuhisa Sakaguchi, Nakae Nakamura, Yukinori Nakata
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Patent number: 6740966Abstract: A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the insulating tape at uniform spaces in a lengthwise direction and electrically connected with the wire patterns, and further includes thick film reinforcing tapes with sprocket holes for transport use provided at uniform spaces, the reinforcing tapes being provided on both side portions of the insulating tape, in the lengthwise direction.Type: GrantFiled: March 7, 2001Date of Patent: May 25, 2004Assignee: Sharp Kabushiki KaishaInventor: Nakae Nakamura
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Patent number: 6650002Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is i formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.Type: GrantFiled: June 21, 2000Date of Patent: November 18, 2003Assignee: Sharp Kabushiki KaishiInventors: Kenji Toyosawa, Atsushi Ono, Yasunori Chikawa, Nobuhisa Sakaguchi, Nakae Nakamura, Yukinori Nakata
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Patent number: 6624520Abstract: A tape carrier in accordance with the present invention is arranged so that it entirely covers one of surfaces of a semiconductor element, and has a metal pattern which is connected to a connection terminal of the semiconductor element an external device. In this arrangement, the metal pattern is exposed to the surface opposite to the surface to which the semiconductor element is connected. With this arrangement, it is possible to connect a circuit element including a semiconductor element to the wiring pattern exposed to the surface on the side opposite to the surface to which the semiconductor element is connected, of the upper and lower two surfaces that the tape carrier has. Moreover, since the metal pattern is exposed to the surface on the side opposite to the surface to which the semiconductor element is connected, a circuit element can be connected also to this surface, and a package circuit is constituted by using both of the surfaces of the tape carrier.Type: GrantFiled: November 21, 2000Date of Patent: September 23, 2003Assignee: Sharp Kabushiki KaishaInventor: Nakae Nakamura
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Patent number: 6441467Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.Type: GrantFiled: April 22, 1998Date of Patent: August 27, 2002Assignee: Sharp Kabushiki KaishaInventors: Kenji Toyosawa, Atsushi Ono, Yasunori Chikawa, Nobuhisa Sakaguchi, Nakae Nakamura, Yukinori Nakata
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Publication number: 20020000659Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.Type: ApplicationFiled: April 22, 1998Publication date: January 3, 2002Inventors: KENJI TOYOSAWA, ATSUSHI ONO, YASUNORI CHIKAWA, NOBUHISA SAKAGUCHI, NAKAE NAKAMURA, YUKINORI NAKATA
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Patent number: 6313526Abstract: A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the insulating tape at uniform spaces in a lengthwise direction and electrically connected with the wire patterns, and further includes thick film reinforcing tapes with sprocket holes for transport use provided at uniform spaces, the reinforcing tapes being provided on both side portions of the insulating tape, in the lengthwise direction.Type: GrantFiled: November 30, 1999Date of Patent: November 6, 2001Assignee: Sharp Kabushiki KaishaInventor: Nakae Nakamura
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Publication number: 20010008303Abstract: A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the insulating tape at uniform spaces in a lengthwise direction and electrically connected with the wire patterns, and further includes thick film reinforcing tapes with sprocket holes for transport use provided at uniform spaces, the reinforcing tapes being provided on both side portions of the insulating tape, in the lengthwise direction.Type: ApplicationFiled: March 7, 2001Publication date: July 19, 2001Applicant: Sharp Kabushiki KaishaInventor: Nakae Nakamura