Patents by Inventor Nalin K. Patel

Nalin K. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5962864
    Abstract: A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The first terminal is patterned into a section and a plurality of layers comprising the mutually separated first and second barrier layers are formed on top of the first terminal. A second terminal is then formed on top of the plurality of semiconductor layers. The second terminal is then patterned so that it only overlies the first terminal in confined region. A front-gate is then formed on top of the patterned second terminal.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mark L. Leadbeater, Nalin K. Patel
  • Patent number: 5701017
    Abstract: A semiconductor device according to the invention is characterized by comprising a heterostructure which comprises an active layer in which carriers can flow within a conduction channel, the heterostructure including a recessed region in which part of the conduction channel is disposed and substantially in the same plane as a pair of side gate, thereby defining a restricted conduction region of the conduction channel.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: December 23, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nalin K. Patel, Jeremy H. Burroughes