Abstract: A semiconductor memory device including a substrate; a mold structure including gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate, intersecting the gate electrodes, and passing through the mold structure; cell contacts connected to the gate electrodes; a first interlayer insulating layer on the mold structure and covering the channel structures and cell contacts; first metal patterns connected to the channel structures, an upper surface of the first metal patterns being coplanar with an upper surface of the first interlayer insulating layer; second metal patterns connected to the cell contacts, an upper surface of the second metal patterns being coplanar with the upper surface of the first metal patterns; a first blocking layer along the upper surface of the first interlayer insulating layer, the first metal patterns, and the second metal patterns; and a first dummy vias passing through the first blocking layer.

Abstract: A semiconductor memory device comprising a substrate including a cell array area and an extension area, a mold structure including, a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate, and a plurality of mold insulating films stacked alternately with the plurality of gate electrodes, a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes, a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes, a first interlayer insulating film on the mold structure so as to cover the plurality of channel structures and the plurality of cell contacts.

Abstract: Phase change memory devices are provided including a selection element electrically connected to a phase change material pattern. The selection element includes a metallic conductor and a semiconductor that are in contact with each other. A depletion region in contact with a metallic pattern is generated in the semiconductor in an equilibrium state. The depletion region includes a high barrier region having an electric potential barrier higher than an interface electric potential barrier and a low barrier region having an electric potential barrier lower than the interface electric potential barrier. Related methods are also provided.

Abstract: Phase change memory devices are provided including a selection element electrically connected to a phase change material pattern. The selection element includes a metallic conductor and a semiconductor that are in contact with each other. A depletion region in contact with a metallic pattern is generated in the semiconductor in an equilibrium state. The depletion region includes a high barrier region having an electric potential barrier higher than an interface electric potential barrier and a low barrier region having an electric potential barrier lower than the interface electric potential barrier. Related methods are also provided.