Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

Abstract: Certain aspects of the present disclosure provide an input clock switching system, including: a clock source configured to output a reference clock signal; a clock generator circuit connected to the clock source and configured to output a plurality of input clock signals based on the reference clock signal; an output clock multiplexer, configured to: receive the plurality of input clock signals; receive an output clock selection signal; and output a first clock signal, wherein the first clock signal is one of the input clock signals; and a glitch suppression circuit, configured to: receive the first clock signal; receive a glitch suppression signal; output a clock output signal, wherein the clock output signal is: the first clock signal when the glitch suppression signal is in a first state; and a logic low signal when the glitch suppression signal is in a second state.

Abstract: A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.

Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

Abstract: Certain aspects of the present disclosure provide an input clock switching system, including: a clock source configured to output a reference clock signal; a clock generator circuit connected to the clock source and configured to output a plurality of input clock signals based on the reference clock signal; an output clock multiplexer, configured to: receive the plurality of input clock signals; receive an output clock selection signal; and output a first clock signal, wherein the first clock signal is one of the input clock signals; and a glitch suppression circuit, configured to: receive the first clock signal; receive a glitch suppression signal; output a clock output signal, wherein the clock output signal is: the first clock signal when the glitch suppression signal is in a first state; and a logic low signal when the glitch suppression signal is in a second state.

Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

Abstract: A power transmission device comprises an engine arranged on a shaft and a first motor. A second motor is arranged on a different shaft from the shaft on which the engine is arranged. A first differential mechanism has a sun gear to which the first motor is connected, a carrier to which the engine is connected, and a ring gear to which the second motor and a drive wheel are connected. A second differential mechanism has a first rotational element to which the first motor is connected, a second rotational element, and a third rotational element to which the engine is connected, and is arranged such that the first motor is located between the first differential mechanism and the second differential mechanism. A case houses the second differential mechanism. A brake mechanism is configured to restrict rotation of the second rotational element and is arranged in the case.

Abstract: A power transmission device comprises an engine and a first motor. A second motor is arranged on a different shaft from a shaft on which the engine is arranged. A first differential mechanism has a sun gear to which the first motor is connected, a carrier to which the engine is connected, and a ring gear to which the second motor and a drive wheel are connected. A second differential mechanism has a first rotational element to which the first motor is connected, a second rotational element, and a third rotational element to which the engine is connected, and is arranged such that the first motor is located between the first differential mechanism and the second differential mechanism. A case houses the second differential mechanism. A brake mechanism is configured to restrict rotation of the second rotational element and is arranged in the case.

Abstract: A downsized drive unit for vehicles having an SOWC is provided. A motor 2 is held in a casing 31 opening toward an axially opposite side of the engine 1, and the opening 31a of the casing 31 is closed by a covering member 32. In order to selectively restrict any of forward and backward rotation of any of rotary members, the SOWC 8 is disposed coaxially with the motor 2 in an inner side of the covering member 32 and attached to the covering member 32.

Abstract: In one embodiment, a method of forming a composite material includes drying organic raw material to remove moisture to less than about 18%. The organic raw material is milled to form organic fiber particles having a size less than about 10 mm. A glue is formed by adding magnesium oxide, magnesium chloride, and water. The glue is mixed with the organic fiber particles to form a slurry. A mold cavity of a mold is filled with the slurry. A pattern is formed by allowing the slurry to set within the mold cavity.

Abstract: The components of a brew/extract of leaves or other parts of the papaya plant (Carica papaya) or fractionated components thereof are effective in the prevention or treatment of stomach cancer, lung cancer, pancreatic cancer, colon cancer or other solid cancers, or lymphoma, leukemia or other blood cancers, and are very safe with few side effects, making their medical significance extremely high. In addition, food compositions comprising a papaya plant (Carica papaya) extract component as an effective ingredient for the prevention or amelioration of cancer are highly expected to become functional foods contributing to the preservation and promotion of human health.

Abstract: Therapeutic methods comprising administering anti-CD26 antibodies for the prevention and treatment of cancers and immune diseases associated with expressing CD26 are provided. The invention describes various types of anti-CD26 antibodies and modes of administration.

Abstract: Therapeutic methods comprising administering a composition comprising CD26 thereof in conjunction with chemotherapeutic agents or radiotherapeutic agents for the prevention and treatment of cancers are provided. Also provided are methods for potentiating immune responses comprising administering a composition comprising CD26.

Abstract: A tuning module tunes a dual frequency PLL synthesized tuner to a desired channel frequency. The dual frequency PLL synthesized tuner includes a first PLL and a second PLL. The tuning module receives a carrier-to-noise ratio ("CNR") for each of one or more signals output from the dual frequency PLL synthesized tuner. The tuning module then generates first PLL parameters and second PLL parameters based on the CNRs and the desired channel frequency. Finally, the tuning module programs the first PLL with the first PLL parameters and programs the second PLL with the second PLL parameters.