Patents by Inventor Nam Ho Hur

Nam Ho Hur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11128509
    Abstract: An apparatus and method for transmitting broadcast signal to which channel bonding is applied are disclosed. The apparatus according to the present invention includes an input formatting unit configured to generate baseband packets corresponding to a plurality of packet types using data corresponding to a physical layer pipe; a stream partitioner configured to partition the baseband packets into a plurality of partitioned streams corresponding to the plurality of packet types; BICM units configured to perform error correction encoding, interleaving and modulation corresponding to the plurality of partitioned streams, respectively; and waveform generators configured to generate RF transmission signals corresponding to the plurality of partitioned streams, respectively.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 21, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Jae-Young Lee, Sun-Hyoung Kwon, Nam-Ho Hur, Heung-Mook Kim
  • Patent number: 11115053
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 7, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Publication number: 20210273657
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Patent number: 11108414
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 31, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11108409
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 31, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11102048
    Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 24, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Jae-Young Lee, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11096182
    Abstract: Disclosed herein are a gateway-signaling method for frequency/timing offsets and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a frequency/timing decision unit for determining a center frequency to which a frequency offset is applied using a carrier offset, which is identified using a timing and a management packet transmitted through a Studio-to-Transmitter Link (STL); and an RF signal generation unit for generating an RF signal to be transmitted, which corresponds to the center frequency.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 17, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae-Young Lee, Sung-Ik Park, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11095323
    Abstract: Disclosed herein are a gateway-signaling method for Multiple-Input Single-Output (MISO) operation and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a predistortion unit for performing predistortion for decorrelating signals corresponding to transmitters using the number of transmitters used for MISO and a transmitter coefficient index that are identified using a timing and management packet transmitted through a Studio-to-Transmitter Link (STL), thereby generating a pre-distorted signal; and an RF signal generation unit for generating an RF transmission signal using the pre-distorted signal corresponding to the transmitter coefficient index.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 17, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae-Young Lee, Sung-Ik Park, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
  • Publication number: 20210250050
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Bo-Mi LIM, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Publication number: 20210250046
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Patent number: 11082063
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Publication number: 20210218993
    Abstract: Disclosed are an image encoding method using a skip mode and a device using the method. The image encoding method may comprise the steps of: judging whether there is residual block data of a prediction target block on the basis of predetermined data indicating whether residual block data has been encoded; and, if there is residual block data, restoring the prediction target block on the basis of the residual block data and an intra-screen predictive value of the prediction target block. Consequently, encoding and decoding efficiency can be increased by carrying out the encoding and decoding of screen residual data only for prediction target blocks where there is a need for a residual data block in accordance with screen similarity.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 15, 2021
    Applicants: Electronics and Telecommunications Research Institute, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Gun BANG, Won Sik CHEONG, Gi Mun UM, Nam Ho HUR, Gwang Hoon PARK, Kyung Yong KIM
  • Publication number: 20210203360
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • Publication number: 20210203359
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • Publication number: 20210194503
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: March 10, 2021
    Publication date: June 24, 2021
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • Patent number: 11038534
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 15, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11032115
    Abstract: Disclosed herein are an apparatus and method for decoding a bootstrap signal. The apparatus for decoding a bootstrap signal according to an embodiment of the present invention includes an operation unit for calculating the relative cyclic shift and the channel gain estimate of a received bootstrap signal and correcting the channel gain estimate using the relative cyclic shift, and a decoding unit for decoding the bootstrap signal using the corrected channel gain estimate.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 8, 2021
    Assignees: Electronics and Telecommunications Research Institute, Korea Maritime University Industry-Academic Cooperation Foundation
    Inventors: Sung-Ik Park, Jeong-Chang Kim, Jae-Young Lee, Sun-Hyoung Kwon, Hyeong-Seok Kim, Heung-Mook Kim, Nam-Ho Hur
  • Publication number: 20210167802
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 3, 2021
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Heung-Mook KIM, Jae-Young LEE, Nam-Ho HUR
  • Publication number: 20210168807
    Abstract: A method for transmitting and receiving slot setting information in a communication system is disclosed. An operating method of a UE comprises the steps of: receiving, from a base station, a first upper layer message including SFI for indicating a format of a slot; receiving, from the base station, DCI or a second upper layer message for indicating a use of a flexible symbol belonging to the slot set by the SFI; and determining the flexible symbol belonging to the slot as a DL symbol or a UL symbol on the basis of the second upper layer message or the DCI. Therefore, a performance of a communication system can be improved.
    Type: Application
    Filed: August 3, 2018
    Publication date: June 3, 2021
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hoi Yoon JUNG, Sung Ik PARK, Heung Mook KIM, Nam Ho HUR
  • Publication number: 20210159921
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR