Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

Abstract: An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.

Abstract: An apparatus for predicting a traffic speed and a method thereof are provided. The apparatus includes an input device that receives traffic speed sequences of a plurality of links and a controller that detects a spatio-temporal relationship between traffic speeds of the plurality of links and predicts a future traffic speed of a target link based on the spatio-temporal relationship between the traffic speeds of the plurality of links.

Abstract: A method for forming through-via metal wiring is disclosed. According to the method, through-via metal wiring can be formed with excellent plating quality without an expensive sputtering process by bonding a metal foil to one side of a substrate having a through-via formed therein and using the foil as a metal seed layer.

Abstract: The present invention relates to a satellite antenna integrated time-synchronization device for generating a time-synchronization signal from a satellite signal received from a satellite, which includes a case, a 1PPS synchronization module which is disposed in the case and is configured to generate at least a 1PPS signal from the satellite signal, and a signal processing means which is disposed in the case and is configured to generate an IRIG signal and communication data using the 1PPS signal input from the 1PPS synchronization module.

Abstract: A signal detecting circuit of an infrared sensor includes: a cell array in which bolometers sensing infrared rays and outputting signal currents are arranged in an N×M format; a level generator that outputs a plurality of bias voltages corresponding to a plurality of bias levels; N resistor non-uniformity correcting circuits that are located in a column direction of the cell array and supply different bias voltages to each of the bolometers; M resistor non-uniformity correcting circuits that are located in a row direction of the cell array and supply different bias voltages to each of the bolometers; a control unit that sets a bias voltage level of each resistor non-uniformity correcting circuit to correct the resistor non-uniformity of the cell array; and N integrators that integrate the signal currents output from the cell array.

Abstract: A signal detecting circuit of an infrared sensor includes: a cell array in which bolometers sensing infrared rays and outputting signal currents are arranged in an N×M format; a level generator that outputs a plurality of bias voltages corresponding to a plurality of bias levels; N resistor non-uniformity correcting circuits that are located in a column direction of the cell array and supply different bias voltages to each of the bolometers; M resistor non-uniformity correcting circuits that are located in a row direction of the cell array and supply different bias voltages to each of the bolometers; a control unit that sets a bias voltage level of each resistor non-uniformity correcting circuit to correct the resistor non-uniformity of the cell array; and N integrators that integrate the signal currents output from the cell array.