Patents by Inventor Namhyun LEE
Namhyun LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074154Abstract: A semiconductor memory may include a substrate, a buried dielectric layer on the substrate and providing a first recess that extends in a first direction, a word line in the first recess of the buried dielectric layer, first and second source/drain patterns on opposite sides of the word line, a channel pattern between the word line and the first recess of the buried dielectric layer and contacting the first and second source/drain patterns, and a bit line electrically connected to the second source/drain pattern and extending in a second direction that intersects the first direction. The channel pattern includes vertical parts and a horizontal part connected to each other. The vertical parts are on opposite lateral surfaces of the word line. The horizontal part is below the word line.Type: ApplicationFiled: March 25, 2023Publication date: February 29, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Seonhaeng LEE, SANGWOO PAE, NAMHYUN LEE
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Publication number: 20240047339Abstract: An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.Type: ApplicationFiled: February 7, 2023Publication date: February 8, 2024Inventors: SEUNGMIN CHA, SEUNGMIN SONG, YOUNGWOO KIM, JINKYU KIM, SORA YOU, NAMHYUN LEE, SUNGMOON LEE
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Publication number: 20240030355Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Seungmin SONG, Taeyong KWON, Jaehyeoung MA, Namhyun LEE
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Publication number: 20230422479Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.Type: ApplicationFiled: April 12, 2023Publication date: December 28, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jeesun Lee, Junsoo Kim, Daehyun Moon, Namhyun Lee, Seonhaeng Lee, Sungho Jang, Joohyun Jeon, Joon Han
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Publication number: 20230402458Abstract: A semiconductor device includes a first transistor structure on a substrate, the first transistor structure including first channel layers spaced apart from each other, a first gate electrode surrounding the first channel layers, a first source/drain region connected to the first channel layers on a first side of the first gate electrode, and a second source/drain region connected to the first channel layers on a second side of the first gate electrode that is opposite to the first side of the first gate electrode, and a second transistor structure on the first transistor structure, the second transistor structure including second channel layers spaced apart from each other, a second gate electrode surrounding the second channel layers, and a third source/drain region connected to the second channel layers on a first side of the second gate electrode.Type: ApplicationFiled: May 11, 2023Publication date: December 14, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinyeong Joe, Hyohoon Byeon, Namhyun Lee, Sungkeun Lim, Yuyeong Jo
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Patent number: 11799036Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.Type: GrantFiled: July 8, 2021Date of Patent: October 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Seungmin Song, Taeyong Kwon, Jaehyeoung Ma, Namhyun Lee
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Publication number: 20230328964Abstract: A semiconductor device includes a first fin pattern protruding from a substrate and extending in a first direction; first and second active layers extending in the first direction on the first fin pattern, the second active layer being at a level higher than a level of the first active layer, the first and second active layers forming a first active layer structure; a first gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, and extending in a second direction; and a second gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, extending in the second direction, and disposed to be parallel to the first gate.Type: ApplicationFiled: December 28, 2022Publication date: October 12, 2023Inventors: Seonhaeng Lee, Sangwoo Pae, Namhyun Lee
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Publication number: 20230087731Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Junggun YOU, Joohee JUNG, Jaehyeoung MA, Namhyun LEE
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Patent number: 11515421Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.Type: GrantFiled: March 18, 2021Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junggun You, Joohee Jung, Jaehyeoung Ma, Namhyun Lee
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Publication number: 20220165887Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.Type: ApplicationFiled: July 8, 2021Publication date: May 26, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Seungmin SONG, Taeyong KWON, Jaehyeoung MA, Namhyun LEE
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Publication number: 20220037521Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.Type: ApplicationFiled: March 18, 2021Publication date: February 3, 2022Inventors: Junggun YOU, Joohee JUNG, Jaehyeoung MA, Namhyun LEE
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Publication number: 20200411515Abstract: An integrated circuit semiconductor device including: a multi-bridge channel type transistor in a first region of a substrate, wherein the multi-bridge channel type transistor includes a nanosheet stack structure on the substrate, a first gate dielectric layer on the nanosheet stack structure, and a first gate electrode on the first gate dielectric layer; and a fin-type transistor in a second region of the substrate, wherein the fin-type transistor includes an active fin on the substrate, a second gate dielectric layer on the active fin, and a second gate electrode on the second gate dielectric layer, wherein a width of the nanosheet stack structure is greater than a width of the active fin.Type: ApplicationFiled: February 4, 2020Publication date: December 31, 2020Inventors: HOJUN KIM, Namhyun LEE