Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Abstract: Provided herein is a composite anode active material including: a porous carbon structure; a first coating layer on the porous carbon structure and including a non-carbonaceous material capable of intercalating and deintercalating lithium; and a second coating layer on the first coating layer and including a carbonaceous material.

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Abstract: Provided are an anode active material for a lithium secondary battery, a method of preparing the same, and a lithium secondary battery containing the same. The present invention provides an anode active material for a lithium secondary battery including: a carbon based particle; a first carbon coating layer positioned on the carbon based particle and including pores; a silicon coating layer positioned on the pores and/or a pore-free surface of the first carbon coating layer; and second carbon coating layer positioned on the silicon coating layer, a method of preparing the same, and a lithium secondary battery containing the same.

Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

Abstract: The present disclosure relates to Salmonella Gallinarum mutant strains and uses thereof. A vaccine composition according to an aspect has no risk of reverting to pathogenicity, has no residual pathogenicity due to detoxification of an endotoxin, and does not cause lesions and bacterial re-isolation, thereby exhibiting significantly improved safety compared to the existing fowl typhoid vaccines. In addition, since the vaccine composition induces a high-level immune response even when administered to young chicks, it may be used regardless of age, and as the vaccine strain may be used as a live vaccine having an excellent protective capability by itself, the vaccine composition may be useful for preventing and alleviating fowl typhoid.

Abstract: The present disclosure relates to Salmonella Gallinarum mutant strains and uses thereof. A vaccine composition according to an aspect has no risk of recovering pathogenicity, has no residual pathogenicity due to detoxification of an endotoxin, and does not cause lesions and bacterial re-isolation, thereby exhibiting significantly improved safety compared to the existing fowl typhoid vaccines. In addition, since the vaccine composition induces a high-level immune response even when administered to young chicks, it may be used regardless of age, and as the vaccine strain may be used as a live vaccine having an excellent protective capability by itself, the vaccine composition may be useful for preventing and alleviating fowl typhoid.

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

Abstract: Provided are an anode active material for a lithium secondary battery, a manufacturing method thereof, and a lithium secondary battery including the same, the anode active material for a lithium secondary battery including: a carbon-based particle; a composite layer positioned on the carbon-based particle and including a silicon particle dispersed in a carbon matrix; and a carbon coating layer positioned on the composite layer.

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Abstract: Provided herein is a composite anode active material including: a porous carbon structure; a first coating layer on the porous carbon structure and including a non-carbonaceous material capable of intercalating and deintercalating lithium; and a second coating layer on the first coating layer and including a carbonaceous material.

Abstract: Provided are an anode active material for a lithium secondary battery, a method of preparing the same, and a lithium secondary battery containing the same. The present invention provides an anode active material for a lithium secondary battery including: a carbon based particle; a first carbon coating layer positioned on the carbon based particle and including pores; a silicon coating layer positioned on the pores and/or a pore-free surface of the first carbon coating layer; and second carbon coating layer positioned on the silicon coating layer, a method of preparing the same, and a lithium secondary battery containing the same.