Abstract: Provided are a film-type semiconductor package and method using test pads shared by output channels, a test device, and a semiconductor device and method using patterns shared by test channels. The semiconductor device includes a film-type semiconductor package and a test device. The film-type semiconductor package outputs test signals through a plurality of test pads. The test device tests the film-type semiconductor package using the test signals. A printed circuit board (PCB) of the test device includes a plurality of common patterns, each of which connects at least two of a plurality of test channels to an input terminal, the test channels connecting the input terminals to the test pins.

Abstract: The present invention is directed to an image processing apparatus and method which is capable of safely processing and storing image data detected by a camera in a car accident. The image processing apparatus has an advantage of more safely preserving the image data, which are detected in occurrence of external impact, even when the black box device is broken due to an external impact, by promptly storing the image data in the nonvolatile and highly impact-resistant detachable memory card. In addition, the image processing apparatus of the present invention has an advantage of effectively preserving emergency-related data even with less power, by supplying power to only devices required to preserve the image data at an emergency. Furthermore, the image processing apparatus of the present invention has an advantage of preventing wasteful power consumption, by setting the apparatus to be operable corresponding to surroundings of the vehicle and extracting only image data for unusual situations.

Abstract: A semiconductor integrated circuit includes a plurality of data output pins, a data processing circuit to generate output signals responsive to an input signal, and an output selection circuit with at least a normal mode and a test mode. A first group of output signals are provided to a first group of data output pins in a first test cycle of the test mode. And a second group of output signals are provided to a second group of data output pins during a second test cycle of the test mode. The semiconductor integrated circuit can be tested by means of a test device having less test pins than the output pins of the semiconductor integrated circuit under test.

Abstract: A film type package includes a base film, a driving integrated circuit mounted on the base film for inputting/outputting signals to/from external circuits, a plurality of signal lines formed on the base film for transmitting the signals between the external circuits and the driving integrated circuit, a plurality of bonding pads formed on the base film such that the plurality of signal lines are connected to the external circuits, wherein the plurality of bonding pads correspond to the plurality of signal lines, and a test line connected to the driving integrated circuit for transmitting test signals outputted from the driving integrated circuit, wherein the test line is spaced apart from an adjacent signal line among the plurality of signal lines by a predetermined distance.

Abstract: Provided are a film-type semiconductor package and method using test pads shared by output channels, a test device, and a semiconductor device and method using patterns shared by test channels. The semiconductor device includes a film-type semiconductor package and a test device. The film-type semiconductor package outputs test signals through a plurality of test pads. The test device tests the film-type semiconductor package using the test signals. A printed circuit board (PCB) of the test device includes a plurality of common patterns, each of which connects at least two of a plurality of test channels to an input terminal, the test channels connecting the input terminals to the test pins.

Abstract: An LCD source driving circuit includes a gray voltage generator and a D/A converter. The gray voltage generator receives reference gray voltages to generate gray voltages having 2n different voltage levels. The D/A converter has 2n conversion paths and selects one gray voltage according to a received n-bit data among the 2n gray voltages to output the selected gray voltage. The source driving circuit may adjust voltage differences between the neighboring conversion paths when testing the D/A converter.

Abstract: A semiconductor integrated circuit comprises a plurality of data output pins, a test pin, a data processing circuit for generating output signals in response to input signals, and an output circuit for outputting the output signals to the data output pins in a normal mode and sequentially outputting each of the output signals to the test pin in response to a clock signal in a test mode. The test device includes only one test pin and the semiconductor integrated circuit may be tested by connecting the test pin of the test device to the test pin of the semiconductor integrated circuit. That is, the test device including only one test pin can test the semiconductor integrated circuit with n output pins.

Abstract: A semiconductor integrated circuit includes a plurality of data output pins, a data processing circuit to generate output signals responsive to an input signal, and an output selection circuit with at least a normal mode and a test mode. A first group of output signals are provided to a first group of data output pins in a first test cycle of the test mode. And a second group of output signals are provided to a second group of data output pins during a second test cycle of the test mode. The semiconductor integrated circuit can be tested by means of a test device having less test pins than the output pins of the semiconductor integrated circuit under test.

Abstract: A semiconductor integrated circuit comprises a plurality of data output pins, a test pin, a data processing circuit for generating output signals in response to input signals, and an output circuit for outputting the output signals to the data output pins in a normal mode and sequentially outputting each of the output signals to the test pin in response to a clock signal in a test mode. The test device includes only one test pin and the semiconductor integrated circuit may be tested by connecting the test pin of the test device to the test pin of the semiconductor integrated circuit. That is, the test device including only one test pin can test the semiconductor integrated circuit with n output pins.