Abstract: Provided is a semiconductor memory device and method of fabricating the semiconductor memory device. A semiconductor memory device includes a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures is formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.

Abstract: The present disclosure provides substrate heat-treating apparatus including a process chamber in which a flat substrate to be heat treated is placed, the process chamber comprising a beam irradiating plate placed below the flat substrate and an infrared transmitting plate placed above the flat substrate; a beam irradiating module for irradiating a laser beam to a lower surface of the flat substrate through the beam irradiating plate; and a gas circulation cooling module for spraying a cooling gas to an upper surface of the infrared transmitting plate, thereby cooling the infrared transmitting plate.

Abstract: The present disclosure discloses a flat substrate heating apparatus including a module support plate having a plurality of unit module regions placed on an upper surface thereof; a plurality of laser light source modules having a plurality of laser light source devices and seated on unit module regions of the module support plate, respectively; a power supply board placed below the module support plate and configured to supply power to the laser light source module; and an electrode terminal electrically connecting the laser light source module and the power supply board while detachably securing them to upper and lower surfaces of the module support plate.

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a doped semiconductor pattern including a body portion and a first protrusion protruding from the body portion in a first direction, a first channel pattern disposed on a top surface of the first protrusion and extending in the first direction, a first memory pattern surrounding a sidewall of the first channel pattern and extending on a sidewall of the first protrusion, and interlayer insulating layers and conductive patterns alternately stacked on each other in the first direction.

Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.

Abstract: A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

Abstract: A semiconductor memory device includes a stacked structure including insulating layers and conductive layers that are alternately disposed in a vertical direction, a first structure including a channel layer that passes through the stacked structure and a memory pattern between the channel layer and the stacked structure, and a second structure including an insulating pattern that is formed along a sidewall of the stacked structure and a gate pattern that is formed on a sidewall of the insulating pattern.

Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.

Abstract: A three-dimeiisioiial semiconductor device including a memory block including a stack structure comprising a second sub stack formed over a first sub stack, a plurality of channel plugs formed through the stack structure, and a separation pattern formed in the memory block.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of conductive patterns and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the substrate to penetrate the stack structure; at least one first slit extending in a second direction substantially horizontal to the substrate while penetrating conductive patterns for select lines among the plurality of conductive patterns; a second slit extending in the second direction while penetrating the conductive patterns for select lines; and a plurality of support structures disposed on a bottom of the second slit, the plurality of support structures penetrating conductive patterns for word lines among the plurality of conductive patterns.

Abstract: The present disclosure relates to a memory device including a first memory block including a first group of cell plugs and a second group of cell plugs, a second memory block including a third group of cell plugs and a fourth group of cell plugs, a connection region located between the first and second memory blocks, a first source select line commonly coupled to the first group of cell plugs and third group of cell plugs, a second source select line coupled to the second group of cell plugs, and a third source select line coupled to the fourth group of cell plugs.

Abstract: A semiconductor integrated circuit device including a semiconductor substrate, a first transistor, an insulation interlayer and a second transistor. The first transistor formed on the semiconductor substrate. The first transistor includes a horizontal channel substantially parallel to a surface of the semiconductor substrate. The insulating interlayer formed on an upper surface of the semiconductor substrate. A contact hole formed through the insulating interlayer. The second transistor including a channel layer formed in the contact hole. Any one of a source and a drain of the second transistor are electrically connected to any one of electrodes of the first transistor.

Abstract: The present discloses includes a memory device including a first vertical plug and a second vertical plug that are arranged to be adjacent to each other, a first select line contacting the first vertical plug, a second select line over a same layer as the first select line and contacting the second vertical plug, and an isolation pattern overlapping with a portion of the first vertical plug and a portion of the second vertical plug and separating the first select line from the second select line.

Abstract: A semiconductor memory device includes a gate stack structure including alternately stacked interlayer insulating layers and conductive layers, a core pillar penetrating the gate stack structure, a channel layer disposed between the core pillar and the gate stack structure, a memory layer disposed between the channel layer and the gate stack structure, and a doped semiconductor part in contact with the gate stack structure. The doped semiconductor part includes a first region surrounding the core pillar up to an interface in contact with the gate stack structure and a second region extending between the memory layer and the core pillar from the first region.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a doped semiconductor pattern including a body portion and a first protrusion protruding from the body portion in a first direction, a first channel pattern disposed on a top surface of the first protrusion and extending in the first direction, a first memory pattern surrounding a sidewall of the first channel pattern and extending on a sidewall of the first protrusion, and interlayer insulating layers and conductive patterns alternately stacked on each other in the first direction.

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a doped semiconductor pattern including a body portion and a first protrusion protruding from the body portion in a first direction, a first channel pattern disposed on a top surface of the first protrusion and extending in the first direction, a first memory pattern surrounding a sidewall of the first channel pattern and extending on a sidewall of the first protrusion, and interlayer insulating layers and conductive patterns alternately stacked on each other in the first direction.

Abstract: Embodiments of the present invention provide a hybrid memory and a hybrid memory manufacturing method including both a volatile memory and a nonvolatile memory on a single substrate so as to increase an operation speed of a semiconductor device and reduce manufacturing cost.

Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.

Abstract: A semiconductor memory device including a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures are formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.