Abstract: Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.

Abstract: Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.

Abstract: A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.

Abstract: In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation.

Abstract: Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

Abstract: There is provided a method and device for reading, writing, or both, data from or to a pattern recognition type optical memory having a light transmittable substrate. Patterns can be formed in the pattern recognition type optical memory from light images representing the data. An optical memory reading device comprises a light source, an image detecting unit for detecting images corresponding to the patterns and generating image signals converted by an optical/electric converter into electric signals. An optical memory writing device comprises a light source, an electric/optical converter for receiving an electric signal corresponding to the data and converting the electric signal into an image signal, and an image generation unit for receiving the light emitted from the light source and the image signal and generating light images corresponding to the image signal, wherein the images are configured to form the patterns on the light transmittable substrate.

Abstract: Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

Abstract: A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

Abstract: A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

Abstract: A floating body memory includes a semiconductor substrate having a cell region and a peripheral circuit region. A floating body cell is located in the cell region and a first floating body is located in the peripheral circuit region of the semiconductor substrate. A peripheral gate pattern is positioned on the first floating body. First source and drain regions are positioned at both sides of the peripheral gate pattern. First leakage shielding patterns are positioned between the first floating body and the first source and drain regions, the first source and drain regions contacting the first floating body. The first leakage shielding patterns may be positioned outside outer edges of the peripheral gate pattern.

Abstract: Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.

Abstract: In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation.

Abstract: Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.

Abstract: A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.

Abstract: Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

Abstract: A floating body memory includes a semiconductor substrate having a cell region and a peripheral circuit region. A floating body cell is located in the cell region and a first floating body is located in the peripheral circuit region of the semiconductor substrate. A peripheral gate pattern is positioned on the first floating body. First source and drain regions are positioned at both sides of the peripheral gate pattern. First leakage shielding patterns are positioned between the first floating body and the first source and drain regions, the first source and drain regions contacting the first floating body. The first leakage shielding patterns may be positioned outside outer edges of the peripheral gate pattern.

Abstract: A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

Abstract: There is provided a method and device for reading, writing, or both, data from or to a pattern recognition type optical memory having a light transmittable substrate. Patterns can be formed in the pattern recognition type optical memory from light images representing the data. An optical memory reading device comprises a light source, an image detecting unit for detecting images corresponding to the patterns and generating image signals converted by an optical/electric converter into electric signals. An optical memory writing device comprises a light source, an electric/optical converter for receiving an electric signal corresponding to the data and converting the electric signal into an image signal, and an image generation unit for receiving the light emitted from the light source and the image signal and generating light images corresponding to the image signal, wherein the images are configured to form the patterns on the light transmittable substrate.

Abstract: A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors comprises a first amplification transistor adapted to receive, amplify, and output a differential input signal. The first amplification transistor is a first vertical transistor comprising a first top and a first bottom, and the first top is a first drain of the first vertical transistor and the first bottom is a first source of the first vertical transistor. The differential amplifier circuit further comprises a current source electrically disposed between the pair of amplification transistors and a second power supply to form a current path between a first power supply and the second power supply.