Abstract: Systems and methods may use machine learning to automate the parameterization process for multi-stage iterative source separation. Seismic signals that are generated by a plurality of sources are received by a plurality of sensors within a field as a blended signal. An automated machine learning model that has been trained on blended and unblended signals determines if the incoming blended signal has a relatively high or low signal to noise ratio and then selects a threshold value based on the detected signal to noise ratio. The blended signal is then separated according to the source of the seismic data. A seismic image based on the separated seismic data is then generated which can then be used to adjust one or more control parameters in a machine or tool within the field.

Abstract: A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.

Abstract: A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.

Abstract: A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.

Abstract: A method of growing III-N material on a silicon substrate including the steps of epitaxially growing a buffer layer of REO material on a silicon substrate, epitaxially growing a layer of REN material on the surface of the buffer, and epitaxially growing a thin protective layer of REO on the surface of the REN material layer. The substrate and structure can then be conveniently transferred to another growth machine in which are performed the steps of transforming or modifying in-situ the REO protective layer to a REN layer with a nitrogen treatment and epitaxially growing a layer of III-N material on the modified protective layer.

Abstract: III-N material grown on a buffer on a substrate that includes one of a single crystal silicon or a single crystal sapphire. A buffer of single crystal alloy, including one of ErxAl1-xN or (RE1yRE21-y)xAl1-xN, is positioned on the substrate. A layer of single crystal III-N material is positioned on the surface of the buffer and the single crystal alloy has a lattice constant substantially crystal lattice matched to the layer of single crystal III-N material. When the III-N material is GaN, the x in the formula for the alloy varies from less than 1 adjacent the substrate to greater than or equal to 0.249 adjacent the layer of single crystal GaN.

Abstract: A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.

Abstract: One embodiment of a method for analyzing the social network data of one or more users can retrieving from a server data indicative of a user interest profile; determining an initial interest set from the user interest profile using a social graph function; determining a user network influence score including both an influence score for a user and one or more user connections; and generating a final user interest profile in response to an iterative combination of the initial interest set and the user network influence score such that in response to a query, the final user interest profile is returned. Preferably, the preferred method returns the final user interest profile from a central computer to a second computer associated with a third party initiating the query.

Abstract: The present invention relates to implantable medical devices, in particular stents, comprising pro-healing poly(ester-amide)s.

Abstract: A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing a plurality of memory modules connected to a memory controller through a memory bus, selecting a starburst topology, and connecting a resonator to the plurality of memory module in dependence upon the selected starburst topology. An additional method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing by a resonator a predetermined discontinuity reducing impedance at a predetermined location in the multi-memory module circuit between at least two memory modules, the multi-memory module circuit having a plurality of components of logically arranged around the predetermined location.

Abstract: A network gateway processor architecture including a scalable array of compute processors that function to convert inbound data packets to outbound data packets, an ingress processor coupleable to a first network to receive the inbound data packets and coupled to provide the inbound data packets to the compute processors, and an egress processor coupleable to a second network and coupled to the compute processors to collect and forward the outbound data packets to the second network. The ingress processor distributes inbound data packets to the compute processors based on a least load value selected from current load values determined for the respective compute processors of the scalable array. The current load values represent estimated processing completion times for the respective compute processors of the scalable array of compute processors.

Abstract: Data processing devices arranged in a redundant manner, with each of the devices including a thermal sensor measuring its operating temperature, are allocated so that data is processed by the coolest available device. In one form of the invention, the same data is stored in two data storage devices to be retrieved from the device having a cooler operating temperature. When the data is to be stored, it may further be stored in the coolest one of a number of storage devices. In other forms of the invention, the data processing devices are, for example, adapter circuits or computer systems accessed by a server.

Abstract: An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.

Abstract: A server appliance self-adaptively configures to the operating parameters of a communications network to enable remote configuration control exclusively via the communications network. The server appliance includes a host computer system including a network interface controller and an operating system, executable by the host computer system, that is configurable by a defined set of network values for transmitting and receiving data packets through the network interface controller without network configuration conflicts. A control program, executable by the host computer system in conjunction with the operating system, determines, on initial start-up and specifically with respect to the communications network, an initial set of network values to configure the operating system.

Abstract: A network media access controller operates as a centralized control point for managing secure data storage in a network-attached data storage subsystem. The network media access controller includes first and second network interfaces. The first network interface is coupleable through a first network connection to a network-attached data storage subsystem including a storage device. The network-attached data storage subsystem is responsive to a data storage command to store first data to the storage device. The second network interface is coupleable through a second network connection to a client computer system. The client computer system selectively provides the data storage command with respect to second data. A network data processor is coupled to the first network interface to provide the data storage command and first data and to the second network interface to receive the data storage command and second data.

Abstract: A secure storage access controller provides for the proxy routing of data transfer requests and responses between network clients and storage servers. The controller includes first and second network interface processors coupleable to client and data storage networks and a plurality of data packet processors coupled to the first and second network interface processors. Each data packet processor is operative to terminate respective client network connections routed to the plurality of data packet processors through the first network interface processor and to establish respective storage network connections through the second network interface processor. The data packet processors provide for the proxy transport of data transfer requests and responses between the client and storage network connections.

Abstract: A network gateway processor architecture including a scalable array of compute processors that function to convert inbound data packets to outbound data packets, an ingress processor coupleable to a first network to receive the inbound data packets and coupled to provide the inbound data packets to the compute processors, and an egress processor coupleable to a second network and coupled to the compute processors to collect and forward the outbound data packets to the second network. The ingress processor distributes inbound data packets to the compute processors based on a least load value selected from current load values determined for the respective compute processors of the scalable array. The current load values represent estimated processing completion times for the respective compute processors of the scalable array of compute processors.

Abstract: A network data processor system includes a plurality of data packet processors coupled through a data switch fabric between network connection processors. The data packet processors each include a data processing engine configured to perform a data processing function over data contained within predetermined data packets. The network connection processors include network interfaces coupleable to external data transmission networks and provide for the selective routing of said predetermined data packets through said data switch fabric to load balance the processing of the predetermined data packets by the plurality of data packet processors. A network control processor is provided to manage the other processors connected to the data switch fabric and to handle predetermined network connection processes. In the preferred embodiments of the present invention the data processing engine is preferably configured to perform hardware encryption and decryption algorithms called for by the IPsec protocol.

Abstract: The invention is a GRF4 nucleic acid molecule and its corresponding protein which has an important role in cell signaling. The invention also includes biologically functional equivalent nucleic acid molecules and proteins. The invention also relates to methods of using these nucleic acid sequences and proteins in medical treatments and drug screening.